用户手册 — National Instruments Printer Accessories 320030-01

目录

• GPIB-1014 User Manual

  1
• Important Information

  3
  • Limited Warranty

    3
  • Copyright

    3
  • Trademarks

    3
  • Warning

    4
• FCC/DOC Radio Frequency Interference Compliance

  5
• Table of Contents

  6
• About This Manual

  12
  • Organization of This Manual

    12
  • Conventions Used in This Manual

    13
  • Related Documentation

    13
  • Customer Communication

    14
• Chapter 1 Introduction

  15
  • What Your Kit Should Contain

    17
  • Optional Equipment

    17
  • Unpacking

    18
• Chapter 2 General Description

  19
  • Electrical Characteristics

    19
  • VMEbus Characteristics

    20
    • VMEbus Slave-Addressing

      20
    • VMEbus Slave-Data

      21
    • VMEbus Master-Direct Memory Access

      23
      • Interrupter

        24
    • Data Transfer Bus (DTB) Requester

      25
      • VMEbus Modules Not Provided

        25
      • Diagnostic Aids

        25
  • Data Transfer Features

    25
    • Programmed I/O Transfers

      26
  • GPIB-1014 Functional Description

    26
• Chapter 3 Configuration and Installation

  34
  • Configuration

    34
    • Access Mode

      36
    • Base Address

      36
      • Set Base Address Using Jumper Block W1

        37
      • Set Base Address Using Compare Address Lines

        37
    • DMA Address Modifier Code Output

      38
    • Other Configuration Parameters

      40
  • Installation

    40
    • Verification of System Compatibility

      40
    • Cabling

      43
    • Verification Testing

      43
• Chapter 4 Register Bit Descriptions

  44
  • Register Map

    44
    • Register Sizes

      45
    • Register Description

      45
      • Register Description Format

        46
  • Interface Registers

    47
    • Data In Register (DIR)

      50
    • Command/Data Out Register (CDOR)

      51
    • Interrupt Status Register 1 (ISR1)

      52
    • Interrupt Mask Register 1 (IMR1)

      52
    • Interrupt Status Register 2 (ISR2)

      58
    • Interrupt Mask Register 2 (IMR2)

      58
    • Serial Poll Status Register (SPSR)

      63
    • Serial Poll Mode Register (SPMR)

      63
    • Address Status Register (ADSR)

      64
    • Address Mode Register (ADMR)

      66
    • Command Pass Through Register (CPTR)

      69
    • Auxiliary Mode Register (AUXMR)

      71
    • Hidden Registers

      77
    • Internal Counter Register (ICR)

      78
    • Parallel Poll Register (PPR)

      79
    • Auxiliary Register A (AUXRA)

      81
    • Auxiliary Register B (AUXRB)

      83
    • Auxiliary Register E (AUXRE)

      85
    • Address Register 0 (ADR0)

      86
    • Address Register (ADR)

      87
    • Address Register 1 (ADR1)

      88
    • End of String Register (EOSR)

      89
  • DMA Registers

    90
    • Address Registers

      92
    • Transfer Count Registers

      93
    • Function Code Registers

      94
    • Device Control Register

      95
    • Operation Control Register

      97
    • Sequence Control Register

      99
    • Channel Control Register

      100
    • Channel Status Register

      102
    • Channel Error Register

      104
    • Channel Priority Register

      105
    • Interrupt Vector Registers

      106
    • General Control Register

      107
    • Configuration Registers

      108
      • Configuration Register 1 (CFG1)

        108
      • Configuration Register 2 (CFG2)

        110
• Chapter 5 Programming Considerations

  112
  • Initialization

    112
  • The GPIB-1014 as GPIB Controller

    114
    • Becoming Controller-In-Charge (CIC) and Active Controller

      114
    • Sending Remote Multiline Messages (Commands)

      115
    • Going from Active to Standby Controller

      115
    • Going from Standby to Active Controller

      115
    • Going from Active to Idle Controller

      116
  • The GPIB-1014 as GPIB Talker and Listener

    117
    • Programmed Implementation of Talker and Listener

      117
    • Addressed Implementation of the Talker and Listener

      117
      • Address Mode 1

        117
      • Address Mode 2

        118
      • Address Mode 3

        118
  • Sending/Receiving Messages

    119
    • Using Direct Memory Access

      119
    • DMA Transfers without the Carry Cycle

      121
    • DMA Transfers with the Carry Cycle

      124
    • Polling During DMAs

      128
    • Sending END or EOS

      128
    • Terminating the Transfer and Checking the Result

      128
    • Terminating on END or EOS

      130
    • Using Programmed I/O

      131
      • Sending and Receiving Data

        131
      • Sending END or EOS

        131
      • Terminating on END or EOS

        131
  • Interrupts

    132
  • Serial Polls

    134
    • Conducting a Serial Poll

      134
    • Responding to a Serial Poll

      134
  • Parallel Polls

    134
    • Conducting a Parallel Poll

      135
    • Responding to a Parallel Poll

      136
• Chapter 6 Theory of Operation

  137
  • VMEbus Interface

    137
    • Data Lines

      137
      • Slave Read and Write Transfers

        137
      • DMA Transfers

        137
    • Control Signals

      138
    • Address

      138
    • Control Equations of Transceivers

      139
  • Address Decoding

    139
  • Clock and Reset Circuitry

    140
  • Configuration Registers

    141
    • Configuration Register 1

      141
    • Configuration Register 2

      143
  • Timing State Machine

    143
    • Slave Cycles

      143
    • DMA Cycles

      144
  • DMA Gating and Control

    145
  • Interrupter

    146
  • DTB Requester and Controller

    146
  • GPIB Synchronization and Interrupt Control

    149
  • 68450 DMAC

    152
    • DMAC Channel Operation

      152
      • Initialization and Transfer Phases

        152
      • Block Termination

        157
  • GPIB Interface

    162
  • Test and Troubleshooting

    163
    • DMA Stand-Alone Testing

      163
    • GPIB Interface Testing

      163
• Chapter 7 Diagnostic and Troubleshooting Test Procedures

  165
  • Interpreting Test Procedures

    165
  • GPIB-1014 Hardware Installation Tests

    166
• Appendix A Hardware Specifications

  174
• Appendix B Parts List and Schematic Diagrams

  176
• Appendix C Sample Programs

  177
• Appendix D Multiline Interface Messages

  198
• Appendix E Operation of the GPIB

  201
  • Types of Messages

    201
  • Talkers, Listeners, and Controllers

    201
  • The Controller-In-Charge and System Controller

    202
  • GPIB Signals and Lines

    202
    • Data Lines

      202
    • Handshake Lines

      202
      • NRFD (not ready for data)

        203
      • NDAC (not data accepted)

        203
      • DAV (data valid)

        203
    • Interface Management Lines

      203
    • ATN (attention)

      203
    • IFC (interface clear)

      203
    • REN (remote enable)

      203
    • SRQ (service request)

      203
    • EOI (end or identify)

      203
  • Physical and Electrical Characteristics

    204
  • Configuration Requirements

    206
  • Related Documents

    207
• Appendix F Mnemonics Key

  208
• Appendix G Customer Communication

  219
• Glossary

  224
• Index

  225
• Figures

  10
  • Figure 1-1. GPIB-1014 Interface Board

    16
  • Figure 2-1. GPIB-1014 with a VMEbus Computer

    27
  • Figure 2-2. GPIB-1014 in a Multiprocessor Application

    28
  • Figure 2-3. GPIB-1014 Block Diagram

    29
  • Figure 3-1. Parts Locator Diagram

    35
  • Figure 3-2. Access Mode After RESET

    36
  • Figure 3-3. Configuration for GPIB-1014 Base Address 2000 (hex)

    37
  • Figure 3-4. Default Settings of AM Code Jumpers W3, W4, and W5

    38
  • Figure 4-1. Interface Registers

    48
  • Figure 4-2. Writing to the Hidden Registers

    49
  • Figure 4-3. DMA Register Memory Map

    91
  • Figure 5-1. DMA Transfer without Carry Cycle

    121
  • Figure 5-2. DMA Transfer with Carry Cycle

    124
  • Figure 6-1. DTB Requester and Controller Flip-Flop Operations

    147
  • Figure 6-2. Array Format for Array Chaining Modes

    159
  • Figure 6-3. Array Format for Linked Chaining Modes

    160
  • Figure E-1. The GPIB Connector and Signal Assignments

    204
  • Figure E-2. Linear Configuration

    205
  • Figure E-3. Star Configuration

    206
• Tables

  11
  • Table 2-1. GPIB-1014 Signals

    19
  • Table 2-2. mPD7210 Internal GPIB Interface Registers

    21
  • Table 2-3. 68450 Internal DMA Registers

    22
  • Table 2-4. GPIB-1014 Configuration Registers

    23
  • Table 2-5. GPIB-1014 IEEE 488 Interface Capabilities

    31
  • Table 2-6. GPIB-1014 IEEE 1014 Interrupter Compliance Levels

    33
  • Table 3-1. Programming Values for Default Settings of W3, W4, and W5

    39
  • Table 3-2. Setting the Address Modifier Code Bits (AM5-AM0)

    39
  • Table 3-3. GPIB-1014 Pin Assignment on VMEbus Connector P1

    41
  • Table 3-4. GPIB-1014 Pin Assignment on VMEbus Connector P2

    42
  • Table 4-1. GPIB-1014 Register Map

    44
  • Table 4-2. Clues to Understanding Mnemonics

    46
  • Table 4-3. Multiline GPIB Commands Recognized by the mPD7210

    69
  • Table 4-4. Auxiliary Command Summary

    72
  • Table 4-5. Auxiliary Commands: Detail Description

    73
  • Table 4-6. Examples for Configuring the PPR

    80
  • Table 4-7. DMAC DMA Channel Register Set

    90
  • Table 6-1. Control Equations of Transceivers

    139
  • Table A-1. Electrical Characteristics

    174
  • Table A-2. Environmental Characteristics

    174
  • Table A-3. Physical Characteristics

    175