用户手册 — Philips 8-bit microcontroller with two-clock 80C51 core UM10109

目录

• 1. Introduction

  3
  • 1.1 Comparison to the P89LPC932 device

    3
  • 1.2 Pin configuration

    5
  • 1.3 Pin description

    7
  • 1.4 Special function registers

    13
  • 1.5 Memory organization

    20
• 2. Clocks

  21
  • 2.1 Enhanced CPU

    21
  • 2.2 Clock definitions

    21
  • 2.3 Clock output

    21
  • 2.4 On-chip RC oscillator option

    22
  • 2.5 Watchdog oscillator option

    22
  • 2.6 External clock input option

    22
  • 2.7 Oscillator Clock (OSCCLK) wake-up delay

    23
  • 2.8 CPU Clock (CCLK) modification: DIVM register

    24
  • 2.9 Low power select

    24
• 3. Interrupts

  24
  • 3.1 Interrupt priority structure

    25
  • 3.2 External Interrupt pin glitch suppression

    25
• 4. I/O ports

  27
  • 4.1 Port configurations

    28
  • 4.2 Quasi-bidirectional output configuration

    28
  • 4.3 Open drain output configuration

    29
  • 4.4 Input-only configuration

    30
  • 4.5 Push-pull output configuration

    30
  • 4.6 Port 0 and Analog Comparator functions

    31
  • 4.7 Additional port features

    31
• 5. Power monitoring functions

  32
  • 5.1 Brownout detection

    32
  • 5.2 Power-on detection

    33
  • 5.3 Power reduction modes

    33
• 6. Reset

  36
  • 6.1 Reset vector

    38
• 7. Timers 0 and 1

  38
  • 7.1 Mode 0

    39
  • 7.2 Mode 1

    40
  • 7.3 Mode 2

    40
  • 7.4 Mode 3

    40
  • 7.5 Mode 6

    40
  • 7.6 Timer overflow toggle output

    42
• 8. Real-time clock system timer

  43
  • 8.1 Real-time clock source

    44
  • 8.2 Changing RTCS1/RTCS0

    44
  • 8.3 Real-time clock interrupt/wake-up

    44
  • 8.4 Reset sources affecting the Real-time clock

    44
• 9. Capture/Compare Unit (CCU)

  46
  • 9.1 CCU Clock (CCUCLK)

    47
  • 9.2 CCU Clock prescaling

    47
  • 9.3 Basic timer operation

    47
  • 9.4 Output compare

    49
  • 9.5 Input capture

    51
  • 9.6 PWM operation

    52
  • 9.7 Alternating output mode

    53
  • 9.8 Synchronized PWM register update

    54
  • 9.9 HALT

    54
  • 9.10 PLL operation

    54
  • 9.11 CCU interrupt structure

    55
• 10. UART

  58
  • 10.1 Mode 0

    58
  • 10.2 Mode 1

    58
  • 10.3 Mode 2

    59
  • 10.4 Mode 3

    59
  • 10.5 SFR space

    59
  • 10.6 Baud Rate generator and selection

    59
  • 10.7 Updating the BRGR1 and BRGR0 SFRs

    60
  • 10.8 Framing error

    60
  • 10.9 Break detect

    61
  • 10.10 More about UART Mode 0

    62
  • 10.11 More about UART Mode 1

    63
  • 10.12 More about UART Modes 2 and 3

    64
  • 10.13 Framing error and RI in Modes 2 and 3 with SM2 = 1

    64
  • 10.14 Break detect

    65
  • 10.15 Double buffering

    65
  • 10.16 Double buffering in different modes

    65
  • 10.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)

    65
  • 10.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)

    66
  • 10.19 Multiprocessor communications

    67
  • 10.20 Automatic address recognition

    68
• 11. I2C interface

  69
  • 11.1 I2C data register

    70
  • 11.2 I2C slave address register

    70
  • 11.3 I2C control register

    71
  • 11.4 I2C Status register

    72
  • 11.5 I2C SCL duty cycle registers I2SCLH and I2SCLL

    72
  • 11.6 I2C operation modes

    73
• 12. Serial Peripheral Interface (SPI)

  83
  • 12.1 Configuring the SPI

    87
  • 12.2 Additional considerations for a slave

    88
  • 12.3 Additional considerations for a master

    88
  • 12.4 Mode change on SS

    88
  • 12.5 Write collision

    89
  • 12.6 Data mode

    89
  • 12.7 SPI clock prescaler select

    93
• 13. Analog comparators

  93
  • 13.1 Comparator configuration

    93
  • 13.2 Internal reference voltage

    95
  • 13.3 Comparator input pins

    95
  • 13.4 Comparator interrupt

    95
  • 13.5 Comparators and power reduction modes

    95
  • 13.6 Comparators configuration example

    96
• 14. Keypad interrupt (KBI)

  97
• 15. Watchdog timer (WDT)

  98
  • 15.1 Watchdog function

    98
  • 15.2 Feed sequence

    99
  • 15.3 Watchdog clock source

    102
  • 15.4 Watchdog Timer in Timer mode

    103
  • 15.5 Power-down operation

    104
  • 15.6 Periodic wake-up from power-down without an external oscillator

    104
• 16. Additional features

  104
  • 16.1 Software reset

    105
  • 16.2 Dual Data Pointers

    105
• 17. Data EEPROM

  105
  • 17.1 Data EEPROM read

    106
  • 17.2 Data EEPROM write

    107
  • 17.3 Hardware reset

    107
  • 17.4 Multiple writes to the DEEDAT register

    107
  • 17.5 Sequences of writes to DEECON and DEEDAT registers

    107
  • 17.6 Data EEPROM Row Fill

    107
  • 17.7 Data EEPROM Block Fill

    108
• 18. Flash memory

  108
  • 18.1 General description

    108
  • 18.2 Features

    108
  • 18.3 Flash programming and erase

    109
  • 18.4 Using Flash as data storage: IAP-Lite

    109
  • 18.5 In-circuit programming (ICP)

    113
  • 18.6 ISP and IAP capabilities of the P89LPC932A1

    113
  • 18.7 Boot ROM

    113
  • 18.8 Power on reset code execution

    114
  • 18.9 Hardware activation of Boot Loader

    114
  • 18.10 In-system programming (ISP)

    115
  • 18.11 Using the In-system programming (ISP)

    115
  • 18.12 In-application programming (IAP)

    118
  • 18.13 IAP authorization key

    118
  • 18.14 Flash write enable

    119
  • 18.15 Configuration byte protection

    119
  • 18.16 IAP error status

    120
  • 18.17 User configuration bytes

    123
  • 18.18 User security bytes

    124
  • 18.19 Boot Vector register

    125
  • 18.20 Boot status register

    125
• 19. Instruction set

  127
• 20. Disclaimers

  131
• 21. Trademarks

  131
• 22. Contents

  132