用户手册 — Samsung M378B5673EH1-CF8

目录

• 1.0 DDR3 Registered DIMM Ordering Information

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• 2.0 Key Features

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• 3.0 Address Configuration

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• 4.0 x64 DIMM Pin Configurations (Front side/Back Side)

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• 5.0 x72 DIMM Pin Configurations (Front side/Back side)

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• 6.0 Pin Description

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• 7.0 SPD and Thermal Sensor for ECC UDIMMs

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• 8.0 Input/Output Functional Description

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  • 8.1 Address Mirroring Feature

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    • 8.1.1 DRAM Pin Wiring Mirroring

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• 9.0 Function Block Diagram:

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  • 9.1 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

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  • 9.2 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

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  • 9.3 2GB, 256Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

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  • 9.4 2GB, 256Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

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• 10.0 Absolute Maximum Ratings

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  • 10.1 Absolute Maximum DC Ratings

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  • 10.2 DRAM Component Operating Temperature Range

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• 11.0 AC & DC Operating Conditions

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  • 11.1 Recommended DC Operating Conditions (SSTL - 15)

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• 12.0 AC & DC Input Measurement Levels

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  • 12.1 AC & DC Logic Input Levels for Single-ended Signals

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  • 12.2 VREF Tolerances

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  • 12.3 AC & DC Logic Input Levels for Differential Signals

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    • 12.3.1 Differential Signals Definition

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    • 12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

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    • 12.3.3 Single-ended Requirements for Differential Signals

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    • 12.3.4 Differential Input Cross Point Voltage

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  • 12.4 Slew Rate Definition for Single-ended Input Signals

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  • 12.5 Slew Rate Definition for Differential Input Signals

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• 13.0 AC & DC Output Measurement Levels

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  • 13.1 Single-ended AC & DC Output Levels

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  • 13.2 Differential AC & DC Output Levels

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  • 13.3 Single-ended Output Slew Rate

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  • 13.4 DIfferential Output Slew Rate

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• 14.0 IDD Specification Definition

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  • 14.1 IDD SPEC Table

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• 15.0 Input/Output Capacitance

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  • 15.1 Non ECC UDIMM

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  • 15.2 ECC UDIMM

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• 16.0 Electrical Characteristics and AC timing

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  • 16.1 Refresh Parameters by Device Density

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  • 16.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

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  • 16.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

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    • 16.3.1 Speed Bin Table Notes

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• 17.0 Timing Parameters by Speed Grade

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  • 17.1 Jitter Notes

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  • 17.2 Timing Parameter Notes

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• 18.0 Physical Dimensions

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  • 18.1 64Mbx16 based 64Mx64 Module (1 Rank)

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  • 18.2 128Mbx8 based 128Mx64/x72 Module (1 Rank)

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  • 18.3 128Mbx8 based 256Mx64/x72 Module (2 Ranks)

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