用户手册 — Texas Instruments Three Input, Thirteen Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VC L

目录

• TABLE OF CONTENTS

  2
• GENERAL DESCRIPTION

  4
• EVALUATION BOARD KIT CONTENTS

  4
• AVAILABLE LMK04816 EVALUATION BOARDS

  4
• AVAILABLE LMK04816 FAMILY DEVICES

  4
• QUICK START

  5
• DEFAULT CODELOADER MODES FOR EVALUATION BOARDS

  6
• EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04816

  7
• 1. START CODELOADER 4 APPLICATION

  7
• 2. SELECT DEVICE

  7
• 3. PROGRAM/LOAD DEVICE

  8
• 4. RESTORING A DEFAULT MODE

  8
• 5. VISUAL CONFIRMATION OF FREQUENCY LOCK

  9
• 6. ENABLE CLOCK OUTPUTS

  9
• PLL LOOP FILTERS AND LOOP PARAMETERS

  11
• PLL 1 LOOP FILTER

  11
• 122.88 MHz VCXO PLL

  11
• PLL2 LOOP FILTER

  12
• EVALUATION BOARD INPUTS AND OUTPUTS

  13
• RECOMMENDED TEST EQUIPMENT

  21
• PROGRAMMING 0-DELAY MODE IN CODELOADER

  22
• OVERVIEW

  22
• DUAL LOOP 0-DELAY MODE EXAMPLES

  22
• Programming Steps

  22
• Details

  22
• SINGLE LOOP 0-DELAY MODE EXAMPLES

  24
• Programming Steps

  24
• Details

  24
• APPENDIX A: CODELOADER USAGE

  26
• PORT SETUP TAB

  26
• CLOCK OUTPUTS TAB

  27
• PLL1 TAB

  29
• Setting the PLL1 VCO Frequency and PLL2 Reference Frequency

  30
• PLL2 TAB

  31
• BITS/PINS TAB

  32
• REGISTERS TAB

  37
• APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS

  38
• PLL1

  38
• 122.88 MHz VCXO Phase Noise

  38
• Clock Output Measurement Technique

  39
• Buffered Phase Noise

  39
• CLOCK OUTPUTS (CLKOUT)

  40
• LMK04816B CLKout Phase Noise

  40
• LMK04816B OSCout Phase Noise

  41
• APPENDIX C: SCHEMATICS

  43
• POWER SUPPLIES

  43
• LMK04816B DEVICE WITH LOOP FILTER AND CRYSTAL CIRCUITS

  44
• REFERENCE INPUTS (CLKIN0, CLKIN1, & CLKIN2), EXTERNAL VCXO (OSCIN) & VCO CIRCUITS

  45
• CLOCK OUTPUTS (OSCOUT0, CLKOUT0 TO CLKOUT3)

  46
• CLOCK OUTPUTS (CLKOUT4 TO CLKOUT7)

  47
• CLOCK OUTPUTS (CLKOUT8 TO CLKOUT11)

  48
• UWIRE HEADER, LOGIC I/O PORTS AND STATUS LEDS

  49
• USB INTERFACE

  50
• APPENDIX D: BILL OF MATERIALS

  51
• APPENDIX E: PCB LAYERS STACKUP

  56
• APPENDIX F: PCB LAYOUT

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• LAYER #1 – TOP

  57
• LAYER #2 – RF GROUND PLANE (INVERTED)

  58
• LAYER #3 – VCC PLANES

  59
• LAYER #4 – GROUND PLANE (INVERTED)

  60
• LAYER # 5 – VCC PLANES 2

  61
• LAYER #6 – BOTTOM

  62
• LAYERS #1 AND 6 – TOP AND BOTTOM (COMPOSITE)

  63
• APPENDIX G: PROPERLY CONFIGURING LPT PORT

  65
• LPT DRIVER LOADING

  65
• CORRECT LPT PORT/ADDRESS

  65
• CORRECT LPT MODE

  66
• APPENDIX H: TROUBLESHOOTING INFORMATION

  67
• CONFIRM COMMUNICATIONS

  67
• CONFIRM PLL1 OPERATION/LOCKING

  67
• CONFIRM PLL2 OPERATION/LOCKING

  68