用户手册 — Texas Instruments UCD3138 Digital Power Factor Correction Pre-regulator Evaluation Module UCD3138PFCEVM-026

目录

• Using the UCD3138PFCEVM-026

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  • 1 Introduction

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  • 2 Description

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    • 2.1 Typical Applications

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    • 2.2 Features

      4
  • 3  Electrical Performance Specifications

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  • 4 Schematics

    6
  • 5 Test Setup

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    • 5.1 Test Equipment

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    • 5.2  Recommended Test Setup

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  • 6 List of Test Points

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  • 7 List of Terminals

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  • 8 Test Procedure

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    • 8.1 Efficiency Measurement Procedure

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    • 8.2 Equipment Shutdown

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  • 9 Performance Data and Typical Characteristic Curves

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    • 9.1 Efficiency

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    • 9.2 Power Factor

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    • 9.3  Input Current at 115 VAC and 60 Hz

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    • 9.4 Input Current at 230 VAC and 50 Hz

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    • 9.5 Output Voltage Ripple

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    • 9.6 Output Turn On

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    • 9.7 Total Harmonic Distortion (THD)

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    • 9.8 Other Waveforms

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  • 10 EVM Assembly Drawing and PCB Layout

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  • 11 List of Materials

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  • 12 Digital PFC Description

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    • 12.1 1PFC Block Diagram

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      • 12.1.1 Single-Phase PFC Block Diagram

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      • 12.1.2 2-Phase PFC Block Diagram

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      • 12.1.3 Bridgeless PFC Block Diagram

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    • 12.2 UCD3138 Pin Definition

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      • 12.2.1 UCD3138 Pin Definition in Single-Phase PFC

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      • 12.2.2 UCD3138 Pin Definition in 2-Phase PFC

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      • 12.2.3 UCD3138 Pin Definition in Bridgeless PFC

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    • 12.3 EVM Hardware – Introduction

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      • 12.3.1 PFC Pre-Regulator Input

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      • 12.3.2 PFC Power Stage

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      • 12.3.3 Non-Isolated UART Interface

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      • 12.3.4 Isolated UART Interface

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      • 12.3.5 Interface Connector of Control Card

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      • 12.3.6 UCD3138 Resource Allocation for PFC Control

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    • 12.4 EVM Firmware – Introduction

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      • 12.4.1 Background Loop

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      • 12.4.2 Voltage Loop Configuration

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      • 12.4.3 Current Loop Configuration

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      • 12.4.4 Interrupts

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    • 12.5 State Machine

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    • 12.6 PFC Control Firmware

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    • 12.7 System Protection

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      • 12.7.1 Cycle-by-Cycle Current Protection (CBC)

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      • 12.7.2 Over-Voltage Protection (OVP)

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    • 12.8 PFC System Control

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      • 12.8.1 Average Current Mode Control

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      • 12.8.2 ZVS and Valley Control

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    • 12.9 Current Feedback Control Compensation Using PID Control

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      • 12.9.1 Loop Compensation from Poles and Zeros in s-Domain

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      • 12.9.2 Feedback Loop Compenstaion Tuning with PID Coefficients

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      • 12.9.3 Feedback Loop Compensation with Multiple-Set of Parameters

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    • 12.10 Voltage Feedback Loop

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  • 13 Evaluating the Single-Phase PFC with GUI

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    • 13.1 Graphical User Interface (GUI)

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    • 13.2 Open the Designer GUI

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    • 13.3 Overview of the Designer GUI

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      • 13.3.1 Monitor

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      • 13.3.2 Status

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      • 13.3.3 Design and Configure

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  • 14 Monitoring, Re-configuring and Re-tuning with Designer GUI

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    • 14.1 Power On and Test Procedure

      48
    • 14.2 Monitoring with GUI

      49
    • 14.3 Configuration and Re-configuring with GUI

      50
    • 14.4 Feedback Control Loop Tuning and Re-Tuning with GUI

      51
      • 14.4.1 Current Loop Evaluation

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      • 14.4.2 Current Loop Re-Tuning

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      • 14.4.3 Voltage Loop Evaluation and Re-tuning

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  • 15 Digital PFC Firmware Development

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  • 16 References

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• Important Notices

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