Intel 253668-032US User Manual
4-38 Vol. 3
PAGING
The PAT is a 64-bit MSR (IA32_PAT; MSR index 277H) comprising eight (8) 8-bit
entries (entry i comprises bits 8i+7:8i of the MSR).
For any access to a physical address, the table combines the memory type specified
for that physical address by the MTRRs with a memory type selected from the PAT.
Table 11-11 in Section 11.12.3 specifies how a memory type is selected from the PAT.
Specifically, it comes from entry i of the PAT, where i is defined as follows:
entries (entry i comprises bits 8i+7:8i of the MSR).
For any access to a physical address, the table combines the memory type specified
for that physical address by the MTRRs with a memory type selected from the PAT.
Table 11-11 in Section 11.12.3 specifies how a memory type is selected from the PAT.
Specifically, it comes from entry i of the PAT, where i is defined as follows:
•
For an access to an entry in a paging structure whose address is in CR3 (e.g., the
PML4 table with IA-32e paging), i = 2*PCD+PWT, where the PCD and PWT values
come from CR3.
PML4 table with IA-32e paging), i = 2*PCD+PWT, where the PCD and PWT values
come from CR3.
•
For an access to a PDE with PAE paging, i = 2*PCD+PWT, where the PCD and PWT
values come from the relevant PDPTE register.
values come from the relevant PDPTE register.
•
For an access to a paging-structure entry X whose address is in another paging-
structure entry Y, i = 2*PCD+PWT, where the PCD and PWT values come from Y.
structure entry Y, i = 2*PCD+PWT, where the PCD and PWT values come from Y.
•
For an access to the physical address that is the translation of a linear address,
i = 4*PAT+2*PCD+PWT, where the PAT, PCD, and PWT values come from the
relevant PTE (if the translation uses a 4-KByte page) or the relevant PDE (if the
translation uses a 2-MByte page or a 4-MByte page).
i = 4*PAT+2*PCD+PWT, where the PAT, PCD, and PWT values come from the
relevant PTE (if the translation uses a 4-KByte page) or the relevant PDE (if the
translation uses a 2-MByte page or a 4-MByte page).
4.9.3
Caching Paging-Related Information about Memory Typing
A processor may cache information from the paging-structure entries in TLBs and
paging-structure caches (see Section 4.10). These structures may include informa-
tion about memory typing. The processor may memory-typing information from the
TLBs and paging-structure caches instead of from the paging structures in memory.
This fact implies that, if software modifies a paging-structure entry to change the
memory-typing bits, the processor might not use that change for a subsequent
translation using that entry or for access to an affected linear address. See Section
4.10.3.2 for how software can ensure that the processor uses the modified memory
typing.
paging-structure caches (see Section 4.10). These structures may include informa-
tion about memory typing. The processor may memory-typing information from the
TLBs and paging-structure caches instead of from the paging structures in memory.
This fact implies that, if software modifies a paging-structure entry to change the
memory-typing bits, the processor might not use that change for a subsequent
translation using that entry or for access to an affected linear address. See Section
4.10.3.2 for how software can ensure that the processor uses the modified memory
typing.
4.10
CACHING TRANSLATION INFORMATION
The Intel-64 and IA-32 architectures may accelerate the address-translation process
by caching data from the paging structures on the processor. Because the processor
does not ensure that the data that it caches are always consistent with the structures
in memory, it is important for software developers to understand how and when the
processor may cache such data. They should also understand what actions software
can take to remove cached data that may be inconsistent and when it should do so.
This section provides software developers information about the relevant processor
operation.
Section 4.10.1 and Section 4.10.2 describe how the processor may cache informa-
tion in translation lookaside buffers (TLBs) and paging-structure caches, respec-
by caching data from the paging structures on the processor. Because the processor
does not ensure that the data that it caches are always consistent with the structures
in memory, it is important for software developers to understand how and when the
processor may cache such data. They should also understand what actions software
can take to remove cached data that may be inconsistent and when it should do so.
This section provides software developers information about the relevant processor
operation.
Section 4.10.1 and Section 4.10.2 describe how the processor may cache informa-
tion in translation lookaside buffers (TLBs) and paging-structure caches, respec-