Intel 253668-032US User Manual
Vol. 3 4-39
PAGING
tively. Section 4.10.3 explains how software can remove inconsistent cached
information by invalidating portions of the TLBs and paging-structure caches. Section
4.10.4 describes special considerations for multiprocessor systems.
information by invalidating portions of the TLBs and paging-structure caches. Section
4.10.4 describes special considerations for multiprocessor systems.
4.10.1
Translation Lookaside Buffers (TLBs)
A processor may cache information about the translation of linear addresses in trans-
lation lookaside buffers (TLBs). In general, TLBs contain entries that map page
numbers to page frames; these terms are defined in Section 4.10.1.1. Section
4.10.1.2 describes how information may be cached in TLBs, and Section 4.10.1.3
gives details of TLB usage. Section 4.10.1.4 explains the global-page feature, which
allows software to indicate that certain translations should receive special treatment
when cached in the TLBs.
lation lookaside buffers (TLBs). In general, TLBs contain entries that map page
numbers to page frames; these terms are defined in Section 4.10.1.1. Section
4.10.1.2 describes how information may be cached in TLBs, and Section 4.10.1.3
gives details of TLB usage. Section 4.10.1.4 explains the global-page feature, which
allows software to indicate that certain translations should receive special treatment
when cached in the TLBs.
4.10.1.1 Page Numbers, Page Frames, and Page Offsets
Section 4.3, Section 4.4.2, and Section 4.5 give details of how the different paging
modes translate linear addresses to physical addresses. Specifically, the upper bits of
a linear address (called the page number) determine the upper bits of the physical
address (called the page frame); the lower bits of the linear address (called the
page offset) determine the lower bits of the physical address. The boundary
between the page number and the page offset is determined by the page size.
Specifically:
modes translate linear addresses to physical addresses. Specifically, the upper bits of
a linear address (called the page number) determine the upper bits of the physical
address (called the page frame); the lower bits of the linear address (called the
page offset) determine the lower bits of the physical address. The boundary
between the page number and the page offset is determined by the page size.
Specifically:
•
32-bit paging:
— If the translation does not use a PTE (because CR4.PSE = 1 and the PS flag is
— If the translation does not use a PTE (because CR4.PSE = 1 and the PS flag is
1 in the PDE used), the page size is 4 MBytes and the page number comprises
bits 31:22 of the linear address.
bits 31:22 of the linear address.
— If the translation does use a PTE, the page size is 4 KBytes and the page
number comprises bits 31:12 of the linear address.
•
PAE paging:
— If the translation does not use a PTE (because the PS flag is 1 in the PDE
— If the translation does not use a PTE (because the PS flag is 1 in the PDE
used), the page size is 2 MBytes and the page number comprises bits 31:21
of the linear address.
of the linear address.
— If the translation does uses a PTE, the page size is 4 KBytes and the page
number comprises bits 31:12 of the linear address.
•
IA-32e paging:
— If the translation does not uses a PTE (because the PS flag is 1 in the PDE
— If the translation does not uses a PTE (because the PS flag is 1 in the PDE
used), the page size is 2 MBytes and the page number comprises bits 47:21
of the linear address.
of the linear address.
— If the translation does use a PTE, the page size is 4 KBytes and the page
number comprises bits 47:12 of the linear address.