Intel 253668-032US User Manual
Vol. 3 4-41
PAGING
entries in memory. See Section 4.10.3.2 for how software can ensure that the
processor uses the modified paging-structure entries.
If the paging structures specify a translation using a page larger than 4 KBytes, some
processors may choose to cache multiple smaller-page TLB entries for that transla-
tion. Each such TLB entry would be associated with a page number corresponding to
the smaller page size (e.g., bits 47:12 of a linear address with IA-32e paging), even
though part of that page number (e.g., bits 20:12) are part of the offset with respect
to the page specified by the paging structures. The upper bits of the physical address
in such a TLB entry are derived from the physical address in the PDE used to create
the translation, while the lower bits come from the linear address of the access for
which the translation is created. There is no way for software to be aware that
multiple translations for smaller pages have been used for a large page.
If software modifies the paging structures so that the page size used for a 4-KByte
range of linear addresses changes, the TLBs may subsequently contain multiple
translations for the address range (one for each page size). A reference to a linear
address in the address range may use either translation. Which translation is used
may vary from one execution to another, and the choice may be implementation-
specific.
processor uses the modified paging-structure entries.
If the paging structures specify a translation using a page larger than 4 KBytes, some
processors may choose to cache multiple smaller-page TLB entries for that transla-
tion. Each such TLB entry would be associated with a page number corresponding to
the smaller page size (e.g., bits 47:12 of a linear address with IA-32e paging), even
though part of that page number (e.g., bits 20:12) are part of the offset with respect
to the page specified by the paging structures. The upper bits of the physical address
in such a TLB entry are derived from the physical address in the PDE used to create
the translation, while the lower bits come from the linear address of the access for
which the translation is created. There is no way for software to be aware that
multiple translations for smaller pages have been used for a large page.
If software modifies the paging structures so that the page size used for a 4-KByte
range of linear addresses changes, the TLBs may subsequently contain multiple
translations for the address range (one for each page size). A reference to a linear
address in the address range may use either translation. Which translation is used
may vary from one execution to another, and the choice may be implementation-
specific.
4.10.1.4 Global Pages
The Intel-64 and IA-32 architectures also allow for global pages when the PGE flag
(bit 7) is 1 in CR4. If the G flag (bit 8) is 1 in a paging-structure entry that maps a
page (either a PTE or a PDE in which the PS flag is 1), any TLB entry cached for a
linear address using that paging-structure entry is considered to be global. Because
the G flag is used only in paging-structure entries that map a page, and because
information from such entries are not cached in the paging-structure caches, the
global-page feature does not affect the behavior of the paging-structure caches.
(bit 7) is 1 in CR4. If the G flag (bit 8) is 1 in a paging-structure entry that maps a
page (either a PTE or a PDE in which the PS flag is 1), any TLB entry cached for a
linear address using that paging-structure entry is considered to be global. Because
the G flag is used only in paging-structure entries that map a page, and because
information from such entries are not cached in the paging-structure caches, the
global-page feature does not affect the behavior of the paging-structure caches.
4.10.2 Paging-Structure
Caches
In addition to the TLBs, a processor may cache other information about the paging
structures in memory.
structures in memory.
4.10.2.1 Caches for Paging Structures
A processor may support any or of all the following paging-structure caches:
•
PML4 cache (IA-32e paging only). Each PML4-cache entry is referenced by a 9-
bit value and is used for linear addresses for which bits 47:39 have that value.
The entry contains information from the PML4E used to translate such linear
addresses:
— The physical address from the PML4E (the address of the page-directory-
bit value and is used for linear addresses for which bits 47:39 have that value.
The entry contains information from the PML4E used to translate such linear
addresses:
— The physical address from the PML4E (the address of the page-directory-
pointer table).