Intel 253668-032US User Manual
10-50 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
mode is not supported in the x2APIC mode. Hence the Destination Format Register
(DFR) is eliminated in x2APIC mode.
The 32-bit logical x2APIC ID field of LDR is partitioned into two sub-fields:
(DFR) is eliminated in x2APIC mode.
The 32-bit logical x2APIC ID field of LDR is partitioned into two sub-fields:
•
Cluster ID (LDR[31:16]): is the address of the destination cluster
•
Logical ID (LDR[15:0]): defines a logical ID of the individual local x2APIC within
the cluster specified by LDR[31:16].
the cluster specified by LDR[31:16].
This layout enables 2^16-1 clusters each with up to 16 unique logical IDs - effec-
tively providing an addressability of ((2^20) - 16) processors in logical destination
mode.
It is likely that processor implementations may choose to support less than 16 bits of
the cluster ID or less than 16-bits of the Logical ID in the Logical Destination Register.
However system software should be agnostic to the number of bits implemented in
the cluster ID and logical ID sub-fields. The x2APIC hardware initialization will ensure
that the appropriately initialized logical x2APIC IDs are available to system software
and reads of non-implemented bits return zero. This is a read-only register that soft-
ware must read to determine the logical x2APIC ID of the processor. Specifically,
software can apply a 16-bit mask to the lowest 16 bits of the logical x2APIC ID to
identify the logical address of a processor within a cluster without needing to know
the number of implemented bits in cluster ID and Logical ID sub-fields. Similarly,
software can create a message destination address for cluster model, by bit-Oring
the Logical X2APIC ID (31:0) of processors that have matching Cluster ID(31:16).
To enable cluster ID assignment in a fashion that matches the system topology char-
acteristics and to enable efficient routing of logical mode lowest priority device inter-
rupts in link based platform interconnects, the LDR are initialized by hardware based
on the value of x2APIC ID upon x2APIC state transitions. Details of this initialization
are provided in
tively providing an addressability of ((2^20) - 16) processors in logical destination
mode.
It is likely that processor implementations may choose to support less than 16 bits of
the cluster ID or less than 16-bits of the Logical ID in the Logical Destination Register.
However system software should be agnostic to the number of bits implemented in
the cluster ID and logical ID sub-fields. The x2APIC hardware initialization will ensure
that the appropriately initialized logical x2APIC IDs are available to system software
and reads of non-implemented bits return zero. This is a read-only register that soft-
ware must read to determine the logical x2APIC ID of the processor. Specifically,
software can apply a 16-bit mask to the lowest 16 bits of the logical x2APIC ID to
identify the logical address of a processor within a cluster without needing to know
the number of implemented bits in cluster ID and Logical ID sub-fields. Similarly,
software can create a message destination address for cluster model, by bit-Oring
the Logical X2APIC ID (31:0) of processors that have matching Cluster ID(31:16).
To enable cluster ID assignment in a fashion that matches the system topology char-
acteristics and to enable efficient routing of logical mode lowest priority device inter-
rupts in link based platform interconnects, the LDR are initialized by hardware based
on the value of x2APIC ID upon x2APIC state transitions. Details of this initialization
are provided in
10.7.2.4 Deriving Logical x2APIC ID from the Local x2APIC ID
In x2APIC mode, the 32-bit logical x2APIC ID, which can be read from LDR, is derived
from the 32-bit local x2APIC ID. Specifically, the 16-bit logical ID sub-field is derived
by shifting 1 by the lowest 4 bits of the x2APIC ID, i.e. Logical ID = 1 << x2APIC
ID[3:0]. The rest of the bits of the x2APIC ID then form the cluster ID portion of the
logical x2APIC ID:
from the 32-bit local x2APIC ID. Specifically, the 16-bit logical ID sub-field is derived
by shifting 1 by the lowest 4 bits of the x2APIC ID, i.e. Logical ID = 1 << x2APIC
ID[3:0]. The rest of the bits of the x2APIC ID then form the cluster ID portion of the
logical x2APIC ID:
Logical x2APIC ID = [(x2APIC ID[31:4] << 16) | (1 << x2APIC ID[3:0])]
The use of lowest 4 bits in x2APIC ID implies that at least 16 APIC IDs are reserved
for logical processors within a socket in multi-socket configurations. If more than 16
APIC IDS are reserved for logical processors in a socket/package then multiple
cluster IDs can exist within the package.
The LDR initialization occurs whenever the x2APIC mode is enabled. This is described
in
for logical processors within a socket in multi-socket configurations. If more than 16
APIC IDS are reserved for logical processors in a socket/package then multiple
cluster IDs can exist within the package.
The LDR initialization occurs whenever the x2APIC mode is enabled. This is described
in
.