Intel 253668-032US User Manual
Vol. 3 10-51
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.7.2.5 Broadcast/Self Delivery Mode
The destination shorthand field of the ICR allows the delivery mode to be by-passed
in favor of broadcasting the IPI to all the processors on the system bus and/or back
to itself (see
in favor of broadcasting the IPI to all the processors on the system bus and/or back
to itself (see
tion shorthands are supported: self, all excluding self, and all including self. The
destination mode is ignored when a destination shorthand is used.
destination mode is ignored when a destination shorthand is used.
10.7.2.6 Lowest Priority Delivery Mode
With lowest priority delivery mode, the ICR is programmed to send an IPI to several
processors on the system bus, using the logical or shorthand destination mechanism
for selecting the processor. The selected processors then arbitrate with one another
over the system bus or the APIC bus, with the lowest-priority processor accepting the
IPI.
For systems based on the Intel Xeon processor, the chipset bus controller accepts
messages from the I/O APIC agents in the system and directs interrupts to the
processors on the system bus. When using the lowest priority delivery mode, the
chipset chooses a target processor to receive the interrupt out of the set of possible
targets. The Pentium 4 processor provides a special bus cycle on the system bus that
informs the chipset of the current task priority for each logical processor in the
system. The chipset saves this information and uses it to choose the lowest priority
processor when an interrupt is received.
For systems based on P6 family processors, the processor priority used in lowest-
priority arbitration is contained in the arbitration priority register (APR) in each local
APIC.
processors on the system bus, using the logical or shorthand destination mechanism
for selecting the processor. The selected processors then arbitrate with one another
over the system bus or the APIC bus, with the lowest-priority processor accepting the
IPI.
For systems based on the Intel Xeon processor, the chipset bus controller accepts
messages from the I/O APIC agents in the system and directs interrupts to the
processors on the system bus. When using the lowest priority delivery mode, the
chipset chooses a target processor to receive the interrupt out of the set of possible
targets. The Pentium 4 processor provides a special bus cycle on the system bus that
informs the chipset of the current task priority for each logical processor in the
system. The chipset saves this information and uses it to choose the lowest priority
processor when an interrupt is received.
For systems based on P6 family processors, the processor priority used in lowest-
priority arbitration is contained in the arbitration priority register (APR) in each local
APIC.
The APR value is computed as follows:
IF (TPR[7:4]
≥
IRRV[7:4]) AND (TPR[7:4]
>
ISRV[7:4])
THEN
APR[7:0]
←
TPR[7:0]
ELSE
APR[7:4]
←
max(TPR[7:4] AND ISRV[7:4], IRRV[7:4])
APR[3:0]
←
0.
Figure 10-22. Arbitration Priority Register (APR)
31
0
7
8
Reserved
Address: FEE0 0090H
Value after reset: 0H
Value after reset: 0H
Arbitration Priority Sub-Class
Arbitration Priority
4 3