Intel 253668-032US User Manual
Vol. 3 12-5
INTEL
®
MMX
™
TECHNOLOGY SYSTEM PROGRAMMING
•
Execute eight MOVQ instructions to save the contents of the MMX0 through
MMX7 registers to memory. An EMMS instruction may then (optionally) be
executed to clear the MMX state in the x87 FPU.
MMX7 registers to memory. An EMMS instruction may then (optionally) be
executed to clear the MMX state in the x87 FPU.
•
Execute eight MOVQ instructions to read the saved contents of MMX registers
from memory into the MMX0 through MMX7 registers.
from memory into the MMX0 through MMX7 registers.
NOTE
The IA-32 architecture does not support scanning the x87 FPU tag
word and then only saving valid entries.
word and then only saving valid entries.
12.4
SAVING MMX STATE ON TASK OR CONTEXT
SWITCHES
When switching from one task or context to another, it is often necessary to save the
MMX state. As a general rule, if the existing task switching code for an operating
system includes facilities for saving the state of the x87 FPU, these facilities can also
be relied upon to save the MMX state, without rewriting the task switch code. This
reliance is possible because the MMX state is aliased to the x87 FPU state (see
Section 12.2, “The MMX State and MMX Register Aliasing”).
With the introduction of the FXSAVE and FXRSTOR instructions and of
SSE/SSE2/SSE3/SSSE3 extensions, it is possible (and more efficient) to create state
saving facilities in the operating system or executive that save the x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3 state in one operation. Section 13.5, “Designing
OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and
SSE/SSE2/SSE3/SSSE3/SSE4 state on Task or Context Switches,” describes how to
design such facilities. The techniques describes in this section can be adapted to
saving only the MMX and x87 FPU state if needed.
MMX state. As a general rule, if the existing task switching code for an operating
system includes facilities for saving the state of the x87 FPU, these facilities can also
be relied upon to save the MMX state, without rewriting the task switch code. This
reliance is possible because the MMX state is aliased to the x87 FPU state (see
Section 12.2, “The MMX State and MMX Register Aliasing”).
With the introduction of the FXSAVE and FXRSTOR instructions and of
SSE/SSE2/SSE3/SSSE3 extensions, it is possible (and more efficient) to create state
saving facilities in the operating system or executive that save the x87
FPU/MMX/SSE/SSE2/SSE3/SSSE3 state in one operation. Section 13.5, “Designing
OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and
SSE/SSE2/SSE3/SSSE3/SSE4 state on Task or Context Switches,” describes how to
design such facilities. The techniques describes in this section can be adapted to
saving only the MMX and x87 FPU state if needed.
12.5
EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING
MMX INSTRUCTIONS
MMX instructions do not generate x87 FPU floating-point exceptions, nor do they
affect the processor’s status flags in the EFLAGS register or the x87 FPU status word.
The following exceptions can be generated during the execution of an MMX instruc-
tion:
affect the processor’s status flags in the EFLAGS register or the x87 FPU status word.
The following exceptions can be generated during the execution of an MMX instruc-
tion:
•
Exceptions during memory accesses:
— Stack-segment fault (#SS).
— General protection (#GP).
— Page fault (#PF).
— Alignment check (#AC), if alignment checking is enabled.
— Stack-segment fault (#SS).
— General protection (#GP).
— Page fault (#PF).
— Alignment check (#AC), if alignment checking is enabled.