Intel 253668-032US User Manual
12-6 Vol. 3
INTEL
®
MMX
™
TECHNOLOGY SYSTEM PROGRAMMING
•
System exceptions:
— Invalid Opcode (#UD), if the EM flag in control register CR0 is set when an
— Invalid Opcode (#UD), if the EM flag in control register CR0 is set when an
MMX instruction is executed (see Section 12.1, “Emulation of the MMX
Instruction Set”).
Instruction Set”).
— Device not available (#NM), if an MMX instruction is executed when the TS
flag in control register CR0 is set. (See Section 13.5.1, “Using the TS Flag to
Control the Saving of the x87 FPU, MMX, SSE, SSE2, SSE3 SSSE3 and SSE4
State.”)
Control the Saving of the x87 FPU, MMX, SSE, SSE2, SSE3 SSSE3 and SSE4
State.”)
•
Floating-point error (#MF). (See Section 12.5.1, “Effect of MMX Instructions on
Pending x87 Floating-Point Exceptions.”)
Pending x87 Floating-Point Exceptions.”)
•
Other exceptions can occur indirectly due to the faulty execution of the exception
handlers for the above exceptions.
handlers for the above exceptions.
12.5.1
Effect of MMX Instructions on Pending x87 Floating-Point
Exceptions
If an x87 FPU floating-point exception is pending and the processor encounters an
MMX instruction, the processor generates a x87 FPU floating-point error (#MF) prior
to executing the MMX instruction, to allow the pending exception to be handled by
the x87 FPU floating-point error exception handler. While this exception handler is
executing, the x87 FPU state is maintained and is visible to the handler. Upon
returning from the exception handler, the MMX instruction is executed, which will
alter the x87 FPU state, as described in Section 12.2, “The MMX State and MMX
Register Aliasing.”
MMX instruction, the processor generates a x87 FPU floating-point error (#MF) prior
to executing the MMX instruction, to allow the pending exception to be handled by
the x87 FPU floating-point error exception handler. While this exception handler is
executing, the x87 FPU state is maintained and is visible to the handler. Upon
returning from the exception handler, the MMX instruction is executed, which will
alter the x87 FPU state, as described in Section 12.2, “The MMX State and MMX
Register Aliasing.”
12.6 DEBUGGING
MMX
CODE
The debug facilities operate in the same manner when executing MMX instructions as
when executing other IA-32 or Intel 64 architecture instructions.
To correctly interpret the contents of the MMX or x87 FPU registers from the
FSAVE/FNSAVE or FXSAVE image in memory, a debugger needs to take account of
the relationship between the x87 FPU register’s logical locations relative to TOS and
the MMX register’s physical locations.
In the x87 FPU context, STn refers to an x87 FPU register at location n relative to the
TOS. However, the tags in the x87 FPU tag word are associated with the physical
locations of the x87 FPU registers (R0 through R7). The MMX registers always refer
to the physical locations of the registers (with MM0 through MM7 being mapped to R0
through R7). Figure 12-2 shows this relationship. Here, the inner circle refers to the
physical location of the x87 FPU and MMX registers. The outer circle refers to the x87
FPU registers’s relative location to the current TOS.
When the TOS equals 0 (case A in Figure 12-2), ST0 points to the physical location
R0 on the floating-point stack. MM0 maps to ST0, MM1 maps to ST1, and so on.
when executing other IA-32 or Intel 64 architecture instructions.
To correctly interpret the contents of the MMX or x87 FPU registers from the
FSAVE/FNSAVE or FXSAVE image in memory, a debugger needs to take account of
the relationship between the x87 FPU register’s logical locations relative to TOS and
the MMX register’s physical locations.
In the x87 FPU context, STn refers to an x87 FPU register at location n relative to the
TOS. However, the tags in the x87 FPU tag word are associated with the physical
locations of the x87 FPU registers (R0 through R7). The MMX registers always refer
to the physical locations of the registers (with MM0 through MM7 being mapped to R0
through R7). Figure 12-2 shows this relationship. Here, the inner circle refers to the
physical location of the x87 FPU and MMX registers. The outer circle refers to the x87
FPU registers’s relative location to the current TOS.
When the TOS equals 0 (case A in Figure 12-2), ST0 points to the physical location
R0 on the floating-point stack. MM0 maps to ST0, MM1 maps to ST1, and so on.