Intel 253668-032US User Manual
2-10 Vol. 3
SYSTEM ARCHITECTURE OVERVIEW
On systems that support IA-32e mode, the extended feature enable register
(IA32_EFER) is available. This model-specific register controls activation of IA-32e
mode and other IA-32e mode operations. In addition, there are several model-
specific registers that govern IA-32e mode instructions:
(IA32_EFER) is available. This model-specific register controls activation of IA-32e
mode and other IA-32e mode operations. In addition, there are several model-
specific registers that govern IA-32e mode instructions:
•
IA32_KernelGSbase — Used by SWAPGS instruction.
•
IA32_LSTAR — Used by SYSCALL instruction.
•
IA32_SYSCALL_FLAG_MASK — Used by SYSCALL instruction.
•
IA32_STAR_CS — Used by SYSCALL and SYSRET instruction.
2.1.7
Other System Resources
Besides the system registers and data structures described in the previous sections,
system architecture provides the following additional resources:
system architecture provides the following additional resources:
•
Operating system instructions (see also: Section 2.7, “System Instruction
Summary”).
Summary”).
•
Performance-monitoring counters (not shown in Figure 2-1).
•
Internal caches and buffers (not shown in Figure 2-1).
Performance-monitoring counters are event counters that can be programmed to
count processor events such as the number of instructions decoded, the number of
interrupts received, or the number of cache loads. See also: Section 20, “Introduc-
tion to Virtual-Machine Extensions.”
The processor provides several internal caches and buffers. The caches are used to
store both data and instructions. The buffers are used to store things like decoded
addresses to system and application segments and write operations waiting to be
performed. See also: Chapter 11, “Memory Cache Control.”
count processor events such as the number of instructions decoded, the number of
interrupts received, or the number of cache loads. See also: Section 20, “Introduc-
tion to Virtual-Machine Extensions.”
The processor provides several internal caches and buffers. The caches are used to
store both data and instructions. The buffers are used to store things like decoded
addresses to system and application segments and write operations waiting to be
performed. See also: Chapter 11, “Memory Cache Control.”
2.2
MODES OF OPERATION
The IA-32 supports three operating modes and one quasi-operating mode:
•
Protected mode — This is the native operating mode of the processor. It
provides a rich set of architectural features, flexibility, high performance and
backward compatibility to existing software base.
provides a rich set of architectural features, flexibility, high performance and
backward compatibility to existing software base.
•
Real-address mode — This operating mode provides the programming
environment of the Intel 8086 processor, with a few extensions (such as the
ability to switch to protected or system management mode).
environment of the Intel 8086 processor, with a few extensions (such as the
ability to switch to protected or system management mode).
•
System management mode (SMM) — SMM is a standard architectural feature
in all IA-32 processors, beginning with the Intel386 SL processor. This mode
provides an operating system or executive with a transparent mechanism for
implementing power management and OEM differentiation features. SMM is
entered through activation of an external system interrupt pin (SMI#), which
generates a system management interrupt (SMI). In SMM, the processor
switches to a separate address space while saving the context of the currently
in all IA-32 processors, beginning with the Intel386 SL processor. This mode
provides an operating system or executive with a transparent mechanism for
implementing power management and OEM differentiation features. SMM is
entered through activation of an external system interrupt pin (SMI#), which
generates a system management interrupt (SMI). In SMM, the processor
switches to a separate address space while saving the context of the currently