Intel 253668-032US User Manual
2-12 Vol. 3
SYSTEM ARCHITECTURE OVERVIEW
The VM flag in the EFLAGS register determines whether the processor is operating in
protected mode or virtual-8086 mode. Transitions between protected mode and
virtual-8086 mode are generally carried out as part of a task switch or a return from
an interrupt or exception handler. See also: Section 17.2.5, “Entering Virtual-8086
Mode.”
The LMA bit (IA32_EFER.LMA.LMA[bit 10]) determines whether the processor is
operating in IA-32e mode. When running in IA-32e mode, 64-bit or compatibility
sub-mode operation is determined by CS.L bit of the code segment. The processor
enters into IA-32e mode from protected mode by enabling paging and setting the
LME bit (IA32_EFER.LME[bit 8]). See also: Chapter 9, “Processor Management and
Initialization.”
The processor switches to SMM whenever it receives an SMI while the processor is in
real-address, protected, virtual-8086, or IA-32e modes. Upon execution of the RSM
instruction, the processor always returns to the mode it was in when the SMI
occurred.
protected mode or virtual-8086 mode. Transitions between protected mode and
virtual-8086 mode are generally carried out as part of a task switch or a return from
an interrupt or exception handler. See also: Section 17.2.5, “Entering Virtual-8086
Mode.”
The LMA bit (IA32_EFER.LMA.LMA[bit 10]) determines whether the processor is
operating in IA-32e mode. When running in IA-32e mode, 64-bit or compatibility
sub-mode operation is determined by CS.L bit of the code segment. The processor
enters into IA-32e mode from protected mode by enabling paging and setting the
LME bit (IA32_EFER.LME[bit 8]). See also: Chapter 9, “Processor Management and
Initialization.”
The processor switches to SMM whenever it receives an SMI while the processor is in
real-address, protected, virtual-8086, or IA-32e modes. Upon execution of the RSM
instruction, the processor always returns to the mode it was in when the SMI
occurred.
2.3
SYSTEM FLAGS AND FIELDS IN THE EFLAGS
REGISTER
The system flags and IOPL field of the EFLAGS register control I/O, maskable hard-
ware interrupts, debugging, task switching, and the virtual-8086 mode (see
Figure 2-4). Only privileged code (typically operating system or executive code)
should be allowed to modify these bits.
The system flags and IOPL are:
TF
ware interrupts, debugging, task switching, and the virtual-8086 mode (see
Figure 2-4). Only privileged code (typically operating system or executive code)
should be allowed to modify these bits.
The system flags and IOPL are:
TF
Trap (bit 8) — Set to enable single-step mode for debugging; clear to
disable single-step mode. In single-step mode, the processor generates a
debug exception after each instruction. This allows the execution state of a
program to be inspected after each instruction. If an application program
sets the TF flag using a POPF, POPFD, or IRET instruction, a debug exception
is generated after the instruction that follows the POPF, POPFD, or IRET.
disable single-step mode. In single-step mode, the processor generates a
debug exception after each instruction. This allows the execution state of a
program to be inspected after each instruction. If an application program
sets the TF flag using a POPF, POPFD, or IRET instruction, a debug exception
is generated after the instruction that follows the POPF, POPFD, or IRET.