Intel 253668-032US User Manual
Vol. 3 16-17
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
a bug to a particular block of code before instruction single-stepping further narrows
the search. If the BTF flag is set when the processor generates a debug exception,
the processor clears the BTF flag along with the TF flag. The debugger must reset the
BTF and TF flags before resuming program execution to continue control-flow single
stepping.
the search. If the BTF flag is set when the processor generates a debug exception,
the processor clears the BTF flag along with the TF flag. The debugger must reset the
BTF and TF flags before resuming program execution to continue control-flow single
stepping.
16.4.4
Branch Trace Messages
Setting the TR flag (bit 6) in the IA32_DEBUGCTL MSR enables branch trace
messages (BTMs). Thereafter, when the processor detects a branch, exception, or
interrupt, it sends a branch record out on the system bus as a BTM. A debugging
device that is monitoring the system bus can read these messages and synchronize
operations with taken branch, interrupt, and exception events.
When interrupts or exceptions occur in conjunction with a taken branch, additional
BTMs are sent out on the bus, as described in Section 16.4.2, “Monitoring Branches,
Exceptions, and Interrupts.”
Unlike the P6 family and Core family processors, the Pentium 4, Atom, and Intel Xeon
processors can collect branch records in the LBR stack MSRs while at the same time
sending/storing BTMs when both the TR and LBR flags are set in the IA32_DEBUGCTL
MSR (in the case of Pentium 4, processor, MSR_DEBUGCTLA).
messages (BTMs). Thereafter, when the processor detects a branch, exception, or
interrupt, it sends a branch record out on the system bus as a BTM. A debugging
device that is monitoring the system bus can read these messages and synchronize
operations with taken branch, interrupt, and exception events.
When interrupts or exceptions occur in conjunction with a taken branch, additional
BTMs are sent out on the bus, as described in Section 16.4.2, “Monitoring Branches,
Exceptions, and Interrupts.”
Unlike the P6 family and Core family processors, the Pentium 4, Atom, and Intel Xeon
processors can collect branch records in the LBR stack MSRs while at the same time
sending/storing BTMs when both the TR and LBR flags are set in the IA32_DEBUGCTL
MSR (in the case of Pentium 4, processor, MSR_DEBUGCTLA).
16.4.5
Branch Trace Store (BTS)
A trace of taken branches, interrupts, and exceptions is useful for debugging code by
providing a method of determining the decision path taken to reach a particular code
location. The LBR flag (bit 0) of IA32_DEBUGCTL provides a mechanism for capturing
records of taken branches, interrupts, and exceptions and saving them in the last
branch record (LBR) stack MSRs, setting the TR flag for sending them out onto the
system bus as BTMs. The branch trace store (BTS) mechanism provides the addi-
tional capability of saving the branch records in a memory-resident BTS buffer, which
is part of the DS save area. The BTS buffer can be configured to be circular so that
the most recent branch records are always available or it can be configured to
generate an interrupt when the buffer is nearly full so that all the branch records can
be saved. The BTINT flag (bit 8) can be used to enable the generation of interrupt
when the BTS buffer is full. See Section 16.4.9.2, “Setting Up the DS Save Area.” for
additional details.
Setting this flag (BTS) alone can greatly reduce the performance of the processor.
CPL-qualified branch trace storing mechanism can help mitigate the performance
impact of sending/logging branch trace messages.
providing a method of determining the decision path taken to reach a particular code
location. The LBR flag (bit 0) of IA32_DEBUGCTL provides a mechanism for capturing
records of taken branches, interrupts, and exceptions and saving them in the last
branch record (LBR) stack MSRs, setting the TR flag for sending them out onto the
system bus as BTMs. The branch trace store (BTS) mechanism provides the addi-
tional capability of saving the branch records in a memory-resident BTS buffer, which
is part of the DS save area. The BTS buffer can be configured to be circular so that
the most recent branch records are always available or it can be configured to
generate an interrupt when the buffer is nearly full so that all the branch records can
be saved. The BTINT flag (bit 8) can be used to enable the generation of interrupt
when the BTS buffer is full. See Section 16.4.9.2, “Setting Up the DS Save Area.” for
additional details.
Setting this flag (BTS) alone can greatly reduce the performance of the processor.
CPL-qualified branch trace storing mechanism can help mitigate the performance
impact of sending/logging branch trace messages.