Intel 253668-032US User Manual
16-18 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.4.6
CPL-Qualified Branch Trace Mechanism
CPL-qualified branch trace mechanism is available to a subset of Intel 64 and IA-32
processors that support the branch trace storing mechanism. The processor supports
the CPL-qualified branch trace mechanism if CPUID.01H:ECX[bit 4] = 1.
The CPL-qualified branch trace mechanism is described in Section 16.4.9.4. System
software can selectively specify CPL qualification to not send/store Branch Trace
Messages associated with a specified privilege level. Two bit fields, BTS_OFF_USR
(bit 10) and BTS_OFF_OS (bit 9), are provided in the debug control register to
specify the CPL of BTMs that will not be logged in the BTS buffer or sent on the bus.
processors that support the branch trace storing mechanism. The processor supports
the CPL-qualified branch trace mechanism if CPUID.01H:ECX[bit 4] = 1.
The CPL-qualified branch trace mechanism is described in Section 16.4.9.4. System
software can selectively specify CPL qualification to not send/store Branch Trace
Messages associated with a specified privilege level. Two bit fields, BTS_OFF_USR
(bit 10) and BTS_OFF_OS (bit 9), are provided in the debug control register to
specify the CPL of BTMs that will not be logged in the BTS buffer or sent on the bus.
16.4.7
Freezing LBR and Performance Counters on PMI
Many issues may generate a performance monitoring interrupt (PMI); a PMI service
handler will need to determine cause to handle the situation. Two capabilities that
allow a PMI service routine to improve branch tracing and performance monitoring
are:
handler will need to determine cause to handle the situation. Two capabilities that
allow a PMI service routine to improve branch tracing and performance monitoring
are:
•
Freezing LBRs on PMI (bit 11)— The processor freezes LBRs on a PMI request
by clearing the LBR bit (bit 0) in IA32_DEBUGCTL. Software must then re-enable
IA32_DEBUGCTL.[0] to continue monitoring branches. When using this feature,
software should be careful about writes to IA32_DEBUGCTL to avoid re-enabling
LBRs by accident if they were just disabled.
by clearing the LBR bit (bit 0) in IA32_DEBUGCTL. Software must then re-enable
IA32_DEBUGCTL.[0] to continue monitoring branches. When using this feature,
software should be careful about writes to IA32_DEBUGCTL to avoid re-enabling
LBRs by accident if they were just disabled.
•
Freezing PMCs on PMI (bit 12) — The processor freezes the performance
counters on a PMI request by clearing the MSR_PERF_GLOBAL_CTRL MSR (see
Figure 30-3). The PMCs affected include both general-purpose counters and
fixed-function counters (see Section 30.4.1, “Fixed-function Performance
Counters”). Software must re-enable counts by writing 1s to the corresponding
enable bits in MSR_PERF_GLOBAL_CTRL before leaving a PMI service routine to
continue counter operation.
counters on a PMI request by clearing the MSR_PERF_GLOBAL_CTRL MSR (see
Figure 30-3). The PMCs affected include both general-purpose counters and
fixed-function counters (see Section 30.4.1, “Fixed-function Performance
Counters”). Software must re-enable counts by writing 1s to the corresponding
enable bits in MSR_PERF_GLOBAL_CTRL before leaving a PMI service routine to
continue counter operation.
Freezing LBRs and PMCs on PMIs occur when:
•
A performance counter had an overflow and was programmed to signal a PMI in
case of an overflow.
— For the general-purpose counters; this is done by setting bit 20 of the
case of an overflow.
— For the general-purpose counters; this is done by setting bit 20 of the
IA32_PERFEVTSELx register.
— For the fixed-function counters; this is done by setting the 3rd bit in the
corresponding 4-bit control field of the MSR_PERF_FIXED_CTR_CTRL register
(see Figure 30-1) or IA32_FIXED_CTR_CTRL MSR (see Figure 30-2).
(see Figure 30-1) or IA32_FIXED_CTR_CTRL MSR (see Figure 30-2).
•
The PEBS buffer is almost full and reaches the interrupt threshold.
•
The BTS buffer is almost full and reaches the interrupt threshold.