Intel 253668-032US User Manual
16-48 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.11 TIME-STAMP
COUNTER
The Intel 64 and IA-32 architectures (beginning with the Pentium processor) define a
time-stamp counter mechanism that can be used to monitor and identify the relative
time occurrence of processor events. The counter’s architecture includes the
following components:
time-stamp counter mechanism that can be used to monitor and identify the relative
time occurrence of processor events. The counter’s architecture includes the
following components:
•
TSC flag — A feature bit that indicates the availability of the time-stamp counter.
The counter is available in an if the function CPUID.1:EDX.TSC[bit 4] = 1.
The counter is available in an if the function CPUID.1:EDX.TSC[bit 4] = 1.
•
IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in P6 family and
Pentium processors) — The MSR used as the counter.
Pentium processors) — The MSR used as the counter.
•
RDTSC instruction — An instruction used to read the time-stamp counter.
•
TSD flag — A control register flag is used to enable or disable the time-stamp
counter (enabled if CR4.TSD[bit 2] = 1).
counter (enabled if CR4.TSD[bit 2] = 1).
The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,
Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and later
processors) is a 64-bit counter that is set to 0 following a RESET of the processor.
Following a RESET, the counter increments even when the processor is halted by the
HLT instruction or the external STPCLK# pin. Note that the assertion of the external
DPSLP# pin may cause the time-stamp counter to stop.
Processor families increment the time-stamp counter differently:
Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and later
processors) is a 64-bit counter that is set to 0 following a RESET of the processor.
Following a RESET, the counter increments even when the processor is halted by the
HLT instruction or the external STPCLK# pin. Note that the assertion of the external
DPSLP# pin may cause the time-stamp counter to stop.
Processor families increment the time-stamp counter differently:
•
For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4
processors, Intel Xeon processors (family [0FH], models [00H, 01H, or 02H]);
and for P6 family processors: the time-stamp counter increments with every
internal processor clock cycle.
The internal processor clock cycle is determined by the current core-clock to bus-
clock ratio. Intel® SpeedStep® technology transitions may also impact the
processor clock.
processors, Intel Xeon processors (family [0FH], models [00H, 01H, or 02H]);
and for P6 family processors: the time-stamp counter increments with every
internal processor clock cycle.
The internal processor clock cycle is determined by the current core-clock to bus-
clock ratio. Intel® SpeedStep® technology transitions may also impact the
processor clock.
•
For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and
higher]); for Intel Core Solo and Intel Core Duo processors (family [06H], model
[0EH]); for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors
(family [06H], model [0FH]); for Intel Core 2 and Intel Xeon processors (family
[06H], display_model [17H]); for Intel Atom processors (family [06H],
display_model [1CH]): the time-stamp counter increments at a constant rate.
That rate may be set by the maximum core-clock to bus-clock ratio of the
processor or may be set by the maximum resolved frequency at which the
processor is booted. The maximum resolved frequency may differ from the
maximum qualified frequency of the processor, see Section 30.10.5 for more
detail.
The specific processor configuration determines the behavior. Constant TSC
behavior ensures that the duration of each clock tick is uniform and supports the
use of the TSC as a wall clock timer even if the processor core changes frequency.
This is the architectural behavior moving forward.
higher]); for Intel Core Solo and Intel Core Duo processors (family [06H], model
[0EH]); for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors
(family [06H], model [0FH]); for Intel Core 2 and Intel Xeon processors (family
[06H], display_model [17H]); for Intel Atom processors (family [06H],
display_model [1CH]): the time-stamp counter increments at a constant rate.
That rate may be set by the maximum core-clock to bus-clock ratio of the
processor or may be set by the maximum resolved frequency at which the
processor is booted. The maximum resolved frequency may differ from the
maximum qualified frequency of the processor, see Section 30.10.5 for more
detail.
The specific processor configuration determines the behavior. Constant TSC
behavior ensures that the duration of each clock tick is uniform and supports the
use of the TSC as a wall clock timer even if the processor core changes frequency.
This is the architectural behavior moving forward.