Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Product codes
P4X-UPE3210-316-6M1333
Page of 326
DRAM Controller Registers (D0:F0)
100
Datasheet
5.2.1
CHDECMISC—Channel Decode Misc
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 111h
Default Value:
00h
Access:
RW/L 
Size:
8 bits
This register provides miscellaneous CHDEC/MAGEN configuration bits.
Bit
Access
Default 
Value
Description
7
RW/L
0b
Reserved 
6:5
RW/L
00b
Enhanced Mode Select (ENHMODESEL): 
00 = Swap Enabled for Bank Selects and Rank Selects
01 = XOR Enabled for Bank Selects and Rank Selects
10 = Swap Enabled for Bank Selects only
11 = XOR Enabled for Bank Select only
This register is locked by ME stolen Memory lock.
4
RW/L
0b
Channel 2 Enhanced Mode (CH2_ENHMODE): 
3
RW/L
0b
Channel 1 Enhanced Mode (CH1_ENHMODE): 
2
RW/L
0b
Channel 0 Enhanced Mode (CH0_ENHMODE): 
1
RW/L
0b
Reserved 
0
RW/L
0b
EP Present (EPPRSNT): This bit indicates whether EP UMA is present in the 
system or not.
This register is locked by ME stolen Memory lock.