Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Intel

Product codes

P4X-UPE3210-316-6M1333

DRAM Controller Registers (D0:F0)

98

Datasheet

5.2

MCHBAR

Table 9.

MCHBAR Register Address Map

Address

Offset

Register Symbol

Register Name

Default

Value

Access

111h

CHDECMISC

Channel Decode Misc

00h

RW/L

200–201h

C0DRB0

Channel 0 DRAM Rank
Boundary Address 0

0000h

RO, RW/L

202–203h

C0DRB1

Channel 0 DRAM Rank
Boundary Address 1

0000h

RW/L, RO

204–205h

C0DRB2

Channel 0 DRAM Rank
Boundary Address 2

0000h

RW/L, RO

206–207h

C0DRB3

Channel 0 DRAM Rank
Boundary Address 3

0000h

RO, RW/L

208–209h

C0DRA01

Channel 0 DRAM Rank 0,1
Attribute

0000h

RW/L

20A

C0DRA23

Channel 0 DRAM Rank 2,3
Attribute

0000h

RW/L

250–251h

C0CYCTRKPCHG

Channel 0 CYCTRK PCHG

0000h

RO, RW

252–255h

C0CYCTRKACT

Channel 0 CYCTRK ACT

00000000h

RW, RO

256–257h

C0CYCTRKWR

Channel 0 CYCTRK WR

0000h

RW

258–25Ah

C0CYCTRKRD

Channel 0 CYCTRK READ

000000h

RO, RW

25B–25Ch

C0CYCTRKREFR

Channel 0 CYCTRK REFR

0000h

RO, RW

260–263h

C0CKECTRL

Channel 0 CKE Control

00000800h

RW, RW/L,

RO

269–26Eh

C0REFRCTRL

Channel 0 DRAM Refresh
Control

021830000C

30h

RW, RO

280–287h

C0ECCERRLOG

Channel 0 ECC Error Log

0000000000

000000h

RO/P, RO

29C–29Fh

C0ODTCTRL

Channel 0 ODT Control

00000000h

RO, RW

600–601h

C1DRB0

Channel 1 DRAM Rank
Boundary Address 0

0000h

RW/L, RO

602–603h

C1DRB1

Channel 1 DRAM Rank
Boundary Address 1

0000h

RO, RW/L

604–605h

C1DRB2

Channel 1 DRAM Rank
Boundary Address 2

0000h

RW/L, RO

606–607h

C1DRB3

Channel 1 DRAM Rank
Boundary Address 3

0000h

RW/L, RO

608–609h

C1DRA01

Channel 1 DRAM Rank 0,1
Attributes

0000h

RW/L

60A–60Bh

C1DRA23

Channel 1 DRAM Rank 2,3
Attributes

0000h

RW/L

650–651h

C1CYCTRKPCHG

Channel 1 CYCTRK PCHG

0000h

RW, RO

652–655h

C1CYCTRKACT

Channel 1 CYCTRK ACT

00000000h

RO, RW

656–657h

C1CYCTRKWR

Channel 1 CYCTRK WR

0000h

RW