Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
96
Datasheet
46
RO
1b
Reserved
45
RO
0b
Primary PCI Express Port x16 Disable (PEX16D):
0 = Capable of x16 PCI Express Port.
1 = Not Capable of x16 PCI Express port; instead PCI Express is limited to x8
0 = Capable of x16 PCI Express Port.
1 = Not Capable of x16 PCI Express port; instead PCI Express is limited to x8
and below. This causes PCI Express port to enable and train logical lanes
[7:0] only. Logical lanes [15:8] are powered down, and the Max Link Width
field of the Link Capability register reports x8 instead of x16. (In the case of
x8 lane reversal, lanes [15:8] are active and lanes [7:0] are powered
down.).
[7:0] only. Logical lanes [15:8] are powered down, and the Max Link Width
field of the Link Capability register reports x8 instead of x16. (In the case of
x8 lane reversal, lanes [15:8] are active and lanes [7:0] are powered
down.).
44
RO
0b
Primary PCI Express Port Disable (PEPD):
0 = There is a PCI Express Port on this MCH. Device 1 and associated memory
0 = There is a PCI Express Port on this MCH. Device 1 and associated memory
spaces are accessible.
1 = There is no PCI Express Port on this MCH. Device 1 and associated memory
and I/O spaces are disabled by hardwiring the D1EN field bit 1 of the Device
Enable register (DEVEN Dev 0 Offset 54h). In addition, Next_Pointer = 00h,
and IO cannot decode to the PCI Express interface. From a Physical Layer
perspective, all 16 lanes are powered down and the link does not attempt to
train.
Enable register (DEVEN Dev 0 Offset 54h). In addition, Next_Pointer = 00h,
and IO cannot decode to the PCI Express interface. From a Physical Layer
perspective, all 16 lanes are powered down and the link does not attempt to
train.
43
RO
0b
Secondary PCI Express Port X16 Disable (PE2X16D):
0 = Capable of x16 PCI Express1 Port.
1 = Not Capable of x16 PCI Express1 port; instead PCI Express1 is limited to x8
0 = Capable of x16 PCI Express1 Port.
1 = Not Capable of x16 PCI Express1 port; instead PCI Express1 is limited to x8
and below. This causes PCI Express1 port to enable and train logical lanes
[7:0] only. Logical lanes [15:8] are powered down, and the Max Link Width
field of the Link Capability register reports x8 instead of x16. (In the case of
x8 lane reversal, lanes [15:8] are active and lanes [7:0] are powered
down.)
[7:0] only. Logical lanes [15:8] are powered down, and the Max Link Width
field of the Link Capability register reports x8 instead of x16. (In the case of
x8 lane reversal, lanes [15:8] are active and lanes [7:0] are powered
down.)
42
RO
0b
Secondary PCI Express Port Disable (PE2PD):
0 = There is a secondary PCI Express Port on this MCH. Device 6 and associated
0 = There is a secondary PCI Express Port on this MCH. Device 6 and associated
memory spaces are accessible.
1 = There is no secondary PCI Express Port on this MCH. Device 6 and
associated memory and IO spaces are disabled by hardwiring the D6EN field
bit [13] of the Device Enable register (DEVEN Dev 0 Offset 54h). All 16 lanes
are powered down and the link does not attempt to train. In addition,
Next_Pointer = 00h, and IO cannot decode to the PCI Express interface.
From a Physical Layer perspective, all 16 lanes are powered down and the
link does not attempt to train.
bit [13] of the Device Enable register (DEVEN Dev 0 Offset 54h). All 16 lanes
are powered down and the link does not attempt to train. In addition,
Next_Pointer = 00h, and IO cannot decode to the PCI Express interface.
From a Physical Layer perspective, all 16 lanes are powered down and the
link does not attempt to train.
41
RO
0b
Reserved
40
RO
0b
ECC Disable (ECCDIS):
0 = ECC capable
1 = Not ECC capable. Hardwires ECC enable field, bit 7, of the CWB Control
0 = ECC capable
1 = Not ECC capable. Hardwires ECC enable field, bit 7, of the CWB Control
Registers (MCHBAR Offset 243h and 643h) to "0".
39
RO
0b
Reserved
38
RO
0b
Reserved
37:35
RO
000b
Reserved
34
RO
0b
Reserved
33:32
RO
00b
Reserved
Bit
Access
Default
Value
Description