Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

97

31:30

RO

00b

DDR Frequency Capability (DDRFC): This field controls which values may be 
written to the Memory Frequency Select field [6:4] of the Clocking Configuration 
registers (MCHBAR Offset C00h). Any attempt to write an unsupported value will 
be ignored.
10 = MCH capable of up to DDR2 800
11 = MCH capable of up to DDR2 667 

29:28

RO

00b

FSB Frequency Capability (FSBFC): This field controls which values are 
allowed in the FSB Frequency Select Field [2:0] of the Clocking Configuration 
Register. These values are determined by the BSEL[2:0] frequency straps. Any 
unsupported strap values will render the MCH System Memory Interface 
inoperable.
00 = MCH capable of "All" Memory Frequencies
01 = MCH capable of up to FSB 1333
10 = MCH capable of up to FSB 1067
11 = MCH capable of up to FSB 800 

27:24

RO

1h

CAPID Version (CAPIDV): This field has the value 0001b to identify the first 
revision of the CAPID register definition. 

23:16

RO

0Ch

CAPID Length (CAPIDL): This field has the value 0Ch to indicate the structure 
length (12 bytes). 

15:8

RO

00h

Next Capability Pointer (NCP): This field is hardwired to 00h indicating the 
end of the capabilities linked list. 

7:0

RO

09h

Capability Identifier (CAP_ID): This field has the value 1001b to identify the 
CAP_ID assigned by the PCI SIG for vendor dependent capability pointers.