Atmel Evaluation Board using the SAM7SE Microcontroller AT91SAM7SE-EK AT91SAM7SE-EK Data Sheet

6295A–ATARM–27-Mar-07

reset_vector:

ldr pc, =reset_handler

undef_vector:

b undef_vector /* Undefined Instruction */

swi_vector:

b swi_vector /* Software Interrupt */

pabt_vector:

ldr pc, =pabt_handler /* Prefetch Abort */

dabt_vector:

ldr pc, =dabt_handler /* Data Abort */

rsvd_vector:

b rsvd_vector /* reserved */

irq_vector:

b irq_handler /* IRQ : read the AIC */

fiq_vector:

b fiq_vector /* FIQ */

The main purpose of the IRQ handler is to fetch the correct jump address for the pending inter-
rupt. This information is held in the Interrupt Vector Register (IVR) of the AIC (see 

 for more information about the AIC). Once the address is loaded, the handler just

branches to it. This is done as follows:

ldr r14, =AT91C_BASE_AIC

ldr r0, [r14, #AIC_IVR]

bx r0

Registers r0 to 12 are not banked, which means they are shared between (almost) all modes.
Since r0-r3 and r12 are defined as scratch registers by the ARM C calling convention, they must
be saved prior to the jump. In addition, r14 contains the interrupt handler return address plus 4,
so it must also be decremented and then saved. The following code saves registers on the stack
and jumps to the interrupt vector:

sub r14, r14, #4

stmfd sp!, {r0-r3, r12, r14}

ldr r14, =AT91C_BASE_AIC

ldr r0, [r14, #AIC_IVR]

bx r0

The final step is to acknowledge the pending interrupt in the AIC (by writing anything in the End
Of Interrupt Command Register), restore registers and then jump back to the main program:

ldr r14, =AT91C_BASE_AIC

str r14, [r14, #AIC_EOICR]

ldmfd sp!, {r0-r3, r12, pc}^

Note that such a handler does not allow for nested interrupts (since IRQs are masked when the
core enters the IRQ mode).

The first step of the initialization process is to configure critical peripherals:

• Embedded Flash Controller (EFC)