Atmel Evaluation Board using the SAM7SE Microcontroller AT91SAM7SE-EK AT91SAM7SE-EK Data Sheet
Product codes
AT91SAM7SE-EK
6
6295A–ATARM–27-Mar-07
Application Note
Oscillator frequency range in MHz:
Oscillator frequency on EK:
Oscillator startup time:
Value for a 2ms startup:
Once the oscillator is started and stabilized, the PLL can be configured. The PLL is made up of
two chained blocks: the first one divides the input clock, while the second one multiplies it. The
MUL and DIV factors are set in the PLL Register (PLLR) of the PMC. These two values must be
chosen according to the main oscillator (input) frequency and the desired main clock (output)
frequency. In addition, the multiplication block has a minimum input frequency, and the master
clock has a maximum allowed frequency; these two constraints have to be taken into account.
The PLL calculator (available on http://www.atmel.com) can be used to compute the best MUL
and DIV values. Example given for the AT91SAM7SE-EK:
two chained blocks: the first one divides the input clock, while the second one multiplies it. The
MUL and DIV factors are set in the PLL Register (PLLR) of the PMC. These two values must be
chosen according to the main oscillator (input) frequency and the desired main clock (output)
frequency. In addition, the multiplication block has a minimum input frequency, and the master
clock has a maximum allowed frequency; these two constraints have to be taken into account.
The PLL calculator (available on http://www.atmel.com) can be used to compute the best MUL
and DIV values. Example given for the AT91SAM7SE-EK:
Like the main oscillator, a PLL startup time must also be provided. Again, it can be calculated by
looking at the DC characteristics given in the datasheet of the corresponding microcontroller.
After PLLR is modified with the PLL configuration values, the software must wait for the PLL to
become locked; this is done by monitoring the Status Register of the PMC.
looking at the DC characteristics given in the datasheet of the corresponding microcontroller.
After PLLR is modified with the PLL configuration values, the software must wait for the PLL to
become locked; this is done by monitoring the Status Register of the PMC.
AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_OUT_0
| (AT91C_CKGR_PLLCOUNT & (40 << 8))
| (AT91C_CKGR_MUL & (72 << 16))
| (AT91C_CKGR_DIV & 14);
while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK));
Finally, the prescaling value of the main clock must be set, and the PLL output selected. Note
that the prescaling value must be set first, to avoid having the chip run at a frequency higher
than the maximum operating frequency defined in the AC characteristics. As such, this step is
done using two register writes, with two loops to wait for the main clock to be ready:
that the prescaling value must be set first, to avoid having the chip run at a frequency higher
than the maximum operating frequency defined in the AC characteristics. As such, this step is
done using two register writes, with two loops to wait for the main clock to be ready:
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
At this point, the chip is configured to run on the main clock with the PLL, at the desired
frequency.
frequency.
3.2.1.6
Low-Level Initialization: Advanced Interrupt Controller
3.2.1.7
Low-Level Initialization: Watchdog
The Watchdog peripheral is enabled by default after a processor reset. If the application does
not use it, which is the case in this example, then it shall be disabled in the Watchdog Mode
Register (WDMR):
not use it, which is the case in this example, then it shall be disabled in the Watchdog Mode
Register (WDMR):
3
f
Osc
20
≤
≤
f
Osc
18.432
MHz
=
1
ms
t
Startup
1.4
ms
≤
≤
OSCOUNT
42000
0.0014
×
8
------------------------------------------
8
=
=
f
Input
18.432
=
DIV
14
=
MUL
73
1
–
(
)
72
=
=
f
Output
18.432
14
------------------
73
×
96.109
MHz
=
=