Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
25
SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
z
Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is
performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters.
After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926
Instruction and the ARM926 Data Masters.
performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters.
After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926
Instruction and the ARM926 Data Masters.
Within the 64 Kbyte SRAM size available, the amount of memory assigned to each block is software programmable
according to Table 7-1.
according to Table 7-1.
7.2.3
Internal ROM
The SAM9M10 embeds an Internal ROM, which contains the bootrom and SAM-BA program.
At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the reset
and before the Remap Command.
and before the Remap Command.
7.2.4
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities the memory layout can be changed with
two parameters.
two parameters.
REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. This is done by software once
the system has boot.
the system has boot.
BMS allows the user to lay out to 0x0, when convenient, the ROM or an external memory. This is done by a hardware
way at reset.
way at reset.
Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these
parameters.
parameters.
The SAM9M10 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal
memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect.
memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface.
7.2.4.1 BMS = 1, boot on embedded ROM
The system boots on Boot Program.
z
Boot on on-chip RC
z
Enable the 32768 Hz oscillator
z
Auto baudrate detection
z
Downloads and runs an application from external storage media into internal SRAM
z
Downloaded code size depends on embedded SRAM size
z
Automatic detection of valid application
z
Bootloader on a non-volatile memory
z
SPI DataFlash/SerialFlash connected on NPCS0 of the SPI0
z
SDCard
z
NandFlash
z
EEPROM connected on TWI0
Table 7-1.
ITCM and DTCM Memory Configuration
SRAM A ITCM size (KBytes)
seen at 0x100000 through AHB
SRAM B DTCM size (KBytes)
seen at 0x200000 through AHB
SRAM C (KBytes)
seen at 0x300000 through AHB
0
0
64
0
64
0
32
32
0