Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Bus Interface Unit
6-2
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
6.1
About the bus interface unit
The ARM926EJ-S Bus Interface Unit (BIU) arbitrates and schedules AHB requests.
The BIU contains separate masters for both instruction and data access enabling
complete AHB system flexibility. Separate masters enable multi-layer AHB (see the
Multi-layer AHB Overview) and multi-AHB systems to be implemented, giving the
benefit of increased overall bus bandwidth and a more flexible system architecture.
Each master is a fully compliant AHB bus master and implements the master functions
as defined in the AMBA Specification (Rev 2.0).
The BIU contains separate masters for both instruction and data access enabling
complete AHB system flexibility. Separate masters enable multi-layer AHB (see the
Multi-layer AHB Overview) and multi-AHB systems to be implemented, giving the
benefit of increased overall bus bandwidth and a more flexible system architecture.
Each master is a fully compliant AHB bus master and implements the master functions
as defined in the AMBA Specification (Rev 2.0).
To increase system performance, write buffers are used to prevent AHB writes stalling
the ARM926EJ-S system. For more details, see Chapter 4 Caches and Write Buffer.
the ARM926EJ-S system. For more details, see Chapter 4 Caches and Write Buffer.
The data BIU AHB signals are prefixed with D, and the instruction BIU signals are
prefixed with I.
prefixed with I.