Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Instruction Memory Barrier
9-2
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
9.1
About the instruction memory barrier operation
Whenever code is treated as data, for example self-modifying code, or loading code into
memory, then a sequence of instructions called an Instruction Memory Barrier (IMB)
operation must be used to ensure consistency between the data and instruction streams
processed by the ARM926EJ-S processor.
memory, then a sequence of instructions called an Instruction Memory Barrier (IMB)
operation must be used to ensure consistency between the data and instruction streams
processed by the ARM926EJ-S processor.
Usually the instruction and data streams are considered to be completely independent
by the ARM926EJ-S processor memory system, and any changes in the data side are
not automatically reflected in the instruction side. For example if code is modified in
main memory then the ICache might contain stale entries. To remove these stale entries
part or all of the ICache must be invalidated.
by the ARM926EJ-S processor memory system, and any changes in the data side are
not automatically reflected in the instruction side. For example if code is modified in
main memory then the ICache might contain stale entries. To remove these stale entries
part or all of the ICache must be invalidated.