Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Instruction Memory Barrier
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
9-3
9.2
IMB operation
To ensure consistency between data and instruction sides, you must take the following
steps:
steps:
1.
2.
3.
4.
5.
9.2.1
Clean the DCache
If the cache contains cache lines corresponding to write-back regions of memory, then
it might contain dirty entries. These entries must be cleaned to make external memory
consistent with the DCache. If only a small part of the cache has to be cleaned, then this
can be done by using a sequence of clean DCache single entry instructions, or if the
entire cache has to be cleaned, then this can be done efficiently using the test and clean
instruction. See Cache Operations Register c7 on page 2-20 for details of cache
maintenance operations.
it might contain dirty entries. These entries must be cleaned to make external memory
consistent with the DCache. If only a small part of the cache has to be cleaned, then this
can be done by using a sequence of clean DCache single entry instructions, or if the
entire cache has to be cleaned, then this can be done efficiently using the test and clean
instruction. See Cache Operations Register c7 on page 2-20 for details of cache
maintenance operations.
9.2.2
Drain the write buffer
Executing a drain write buffer instruction causes the ARM9EJ-S core to wait until
outstanding buffered writes have completed on the AHB interface. This includes writes
that occur as a result of data being written back to main memory because of clean
operations, and data for store instructions.
outstanding buffered writes have completed on the AHB interface. This includes writes
that occur as a result of data being written back to main memory because of clean
operations, and data for store instructions.
9.2.3
Synchronize data and instruction streams in level two AHB subsystems
The level two AHB subsystem might also require explicit synchronization between data
and instruction sides. It is possible for the data and instruction AHB masters to be
attached to different AHB subsystems. Even if both masters are present on the same bus,
some form of separate ICache might exist for performance reasons, and this has to be
invalidated to ensure consistency.
and instruction sides. It is possible for the data and instruction AHB masters to be
attached to different AHB subsystems. Even if both masters are present on the same bus,
some form of separate ICache might exist for performance reasons, and this has to be
invalidated to ensure consistency.
The process of synchronizing instructions and data in level two memory must be
invoked using some form of fully blocking operation. This is to ensure that the end of
the operation can be determined using software. It is recommended that either a
nonbuffered store (
invoked using some form of fully blocking operation. This is to ensure that the end of
the operation can be determined using software. It is recommended that either a
nonbuffered store (
STR
) or a noncached load (
LDR
) is used to trigger external
synchronization.