Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Programmer’s Model
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
2-3
2.2
Summary of ARM926EJ-S system control coprocessor (CP15) registers
CP15 defines 16 registers. Table 2-1 shows the read and write functions of the registers.
Table 2-1 CP15 register summary
Register
Reads
Writes
0
ID code
a
a. Register locations 0, 5, and 13 each provide access to more than one register. The register
accessed depends on the value of the
Opcode_2
field.
Unpredictable
0
Cache type
a
Unpredictable
0
TCM status
a
Unpredictable
1
Control
Control
2
Translation table base
Translation table base
3
Domain access control
Domain access control
4
Reserved
Reserved
5
Data fault status
a
Data fault status
a
5
Instruction fault status
a
Instruction fault status
a
6
Fault address
Fault address
7
Cache operations
Cache operations
8
Unpredictable
TLB operations
9
Cache lockdown
b
b. Register location 9 provides access to more than one register. The register accessed depends
on the value of the
CRm
field. See the register descriptions for details.
Cache lockdown
9
TCM region
TCM region
10
TLB lockdown
TLB lockdown
11 and 12
Reserved
Reserved
13
FCSE PID
a
FCSE PID
a
13
Context ID
a
Context ID
a
14
Reserved
Reserved
15
Test configuration
Test configuration