Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
1087
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
46.6 Functional Description
The LCD module integrates the following digital blocks:
DMA Engine Address Generation (DEAG). This block performs data prefetch and requests access to the AHB
interface.
interface.
Input FIFO, stores the stream of pixels.
Color Lookup Table (CLUT). These 256 RAM-based lookup table entries are selected when the color depth is set
to 1, 2, 4 or 8 bpp.
to 1, 2, 4 or 8 bpp.
Chroma Upsampling Engine (CUE). This block is selected when the input image sampling format is YUV (Y’CbCr)
4:2:0 and converts it to higher quality 4:4:4 image.
4:2:0 and converts it to higher quality 4:4:4 image.
Color Space Conversion (CSC), changes the color space from YUV to RGB.
Two Dimension Scaler (2DSC), resizes the image.
Global Alpha Blender (GAB), performs programmable 256 level alpha blending.
Output FIFO, stores the pixel prior to display.
LCD Timing Engine, provides a fully programmable HSYNC-VSYNC interface.
The DMA controller reads the image through the AHB master interface. The LCD controller engine formats the display
data, then the GAB performs alpha blending if required, and writes the final pixel into the output FIFO. The
programmable timing engine drives a valid pixel onto the LCD_DAT[23:0] display bus.
data, then the GAB performs alpha blending if required, and writes the final pixel into the output FIFO. The
programmable timing engine drives a valid pixel onto the LCD_DAT[23:0] display bus.
46.6.1 Timing Engine Configuration
46.6.1.1 Pixel Clock Period Configuration
The pixel clock (PCLK) generated by the timing engine is the source clock (SCLK) divided by the field CLKDIV in the
LCDC_LCDCFG0 register. The source clock can be selected between the system clock and the 2x system clock with the
field CLKSEL located in the LCDC_LCDCFG0 register. The Pixel Clock period formula is given below:
LCDC_LCDCFG0 register. The source clock can be selected between the system clock and the 2x system clock with the
field CLKSEL located in the LCDC_LCDCFG0 register. The Pixel Clock period formula is given below:
The Pixel Clock polarity is also programmable.
46.6.1.2 Horizontal and Vertical Synchronization Configuration
The following fields are used to configure the timing engine:
HSPW field
VSPW field
VFPW field
VBPW field
HFPW field
HBPW field
PPL field
RPF field
The polarity of output signals is also programmable.
PCLK
SCLK
CLKDIV 2
+
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