Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
1088
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
46.6.1.3 Timing Engine Power Up Software Operation
The following sequence is used to enable the display:
1.
Configure LCD timing parameters, signal polarity and clock period.
2.
Enable the Pixel Clock by writing one to the CLKEN field of the LCDC_LCDEN register.
3.
Poll CLKSTS field of the LCDC_LCDSR register to check that the clock is running.
4.
Enable Horizontal and Vertical Synchronization by writing one to the SYNCEN field of the LCDC_LCDEN register.
5.
Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is up.
6.
Enable the display power signal writing one to the DISPEN field of the LCDC_LCDEN register.
7.
Poll DISPSTS field of the LCDC_LCDSR register to check that the power signal is activated.
The GUARDTIME field of the LCDC_LCDCFG5 register is used to configure the number of frames before the assertion
of the DISP signal.
of the DISP signal.
46.6.1.4 Timing Engine Power Down Software Operation
The following sequence is used to disable the display:
1.
Disable the DISP signal writing DISPDIS field of the LCDC_LCDDIS register.
2.
Poll DISPSTS field of the LCDC_LCDSR register to verify that the DISP is no longer activated.
3.
Disable the hsync and vsync signals by writing one to SYNCDIS field of the LCDC_LCDDIS register.
4.
Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is off.
5.
Disable the Pixel clock by writing one in the CLKDIS field of the LCDC_LCDDIS register.
46.6.2 DMA Software Operations
46.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure
The DMA Channel Descriptor (DSCR) must be word aligned.
The DMA Channel Descriptor structure contains three fields:
DSCR.CHXADDR: Frame Buffer base address register
DSCR.CHXCTRL: Transfer Control register
DSCR.CHXNEXT: Next Descriptor Address register
46.6.2.2 Programming a DMA Channel
1.
Check the status of the channel reading the CHXCHSR register.
2.
Write the channel descriptor (DSCR) structure in the system memory by writing DSCR.CHXADDR Frame base
address, DSCR.CHXCTRL channel control and DSCR.CHXNEXT next descriptor location.
address, DSCR.CHXCTRL channel control and DSCR.CHXNEXT next descriptor location.
3.
If more than one descriptor is expected, the DFETCH field of DSCR.CHXCTRL is set to one to enable the descrip-
tor fetch operation.
tor fetch operation.
4.
Write the DSCR.CHXNEXT register with the address location of the descriptor structure and set DFETCH field of
the DSCR.CHXCTRL register to one.
the DSCR.CHXCTRL register to one.
5.
Enable the relevant channel by writing one to the CHEN field of the CHXCHER register.
6.
An interrupt may be raised if unmasked when the descriptor has been loaded.
Table 46-4. DMA Channel Descriptor Structure
System Memory
Structure Field for channel CHX
DSCR + 0x0
ADDR
DSCR + 0x4
CTRL
DSCR + 0x8
NEXT