Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet

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SAM9X35 [DATASHEET]

11055E–ATARM–10-Mar-2014

In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a
low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver
waits for the next start bit. Synchronous mode operations provide a high speed transfer capability.

Configuration fields and bits are the same as in asynchronous mode.

When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit
in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit
is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing
the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.

Manchester

encoded

data

default polarity

unipolar output

Txd

ASK Modulator

Output

Uptstream Frequency F0

NRZ stream

1

0

0

1

Manchester

encoded

data

default polarity

unipolar output

Txd

FSK Modulator

Output

Uptstream Frequencies 

[F0, F0+offset]

NRZ stream

1

0

0

1

D0

D1

D2

D3

D4

D5

D6

D7

RXD

Start 

Sampling

Parity Bit

Stop Bit

Example: 8-bit, Parity Enabled 1 Stop

Baud Rate

Clock