Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1026
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
46.5
Secure Hash Algorithm (SHA) User Interface
Table 46-2. Register Mapping
Offset
Register
Name
Access
Reset
0x00
Control Register
SHA_CR
Write-only
–
0x04
Mode Register
SHA_MR
Read-write
0x0000100
0x08-0x0C
Reserved
–
–
–
0x10
Interrupt Enable Register
SHA_IER
Write-only
–
0x14
Interrupt Disable Register
SHA_IDR
Write-only
–
0x18
Interrupt Mask Register
SHA_IMR
Read-only
0x0
0x1C
Interrupt Status Register
SHA_ISR
Read-only
0x0
0x20-0x3C
Reserved
–
0x40
Input Data 0 Register
SHA_IDATAR0
Write-only
–
...
...
...
...
...
0x7C
Input Data 15 Register
SHA_IDATAR15
Write-only
–
0x80
Output Data 0 Register
SHA_ODATAR0
Read-only
0x0
...
...
...
...
0x9C
Output Data 7 Register
SHA_ODATAR7
Read-only
0x0
0x94-0xFC
Reserved
–
–
–