Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

1024

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

Auto Mode is similar to Manual Mode, except that in this mode, as soon as the correct number of Input Data Registers is
written, processing is automatically started without any action in the control register.

The DMA can be used in association with the SHA to perform the algorithm on a complete message without any action
by the software during processing.

The SMOD field of the SHA_MR must be set to 0x2.

The DMA must be configured with non incremental addresses.

The start address of any transfer descriptor must be set to point to the SHA_IDATAR0 register.

The DMA chunk size must be set to transfer, for each trigger request, 16 words of 32 bits when processing
SHA1/SHA256 algorithms or 32 words of 32 bits when SHA384/SHA512 are being used.

In ARM processor based products, the AHB bus and processors manipulate data in Little Endian form. However,
following the protocol of FIPS 180-2 specification, data is collected, processed and stored by the SHA module in a Big
Endian form. The data presented to the SHA module (written to SHA_IDATAxR) must be in Little Endian form. The data
read from the SHA module (read from SHA_ODATAxR) will be in Little Endian form.

The SHA interface automatically converts into Big Endian format words that are presented into Little Endian. Likewise,
the SHA interface returns hash results into Little Endian format even if the internal processing is Big Endian.

Managing how data is presented to the SHA registers should be managed by software.

As a clarification of this process consider the following example.

If th e f irst  6 4 b its  o f a me ssa ge (acc ording to FIPS180-2,  i.e.  Big  End ian fo rm at) to be proc ess ed is
0xcafe_dede_0123_4567 then the SHA_IDATA0R and SHA_IDATA1R registers should be written with the following
pattern:



SHA_IDATA0R = 0xefac



SHA_IDATA1R = 0xeded

In a Little Endian system, the message starting with pattern 0xcafe_dede_0123_4567 will be stored into memories as
follows: 



0xca stored at initial offset (for example 0x00),



then 0xfe stored at initial offset + 1 (i.e. 0x01),



0xde stored at initial offset + 2 (i.e. 0x02),



0xde stored at initial offset +3 (i.e. 0x03).

DATRDY

Enable DMA Channels associated with SHA_IDATARx registers

Message Processing  (Multiple Block)

BTC/
channel 0

Message fully processed 
SHA result  can be read

Write accesses into SHA_IDATARx 

Message fully transferred