Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1068
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Notes: 1. SSC4 and SSC7 timings depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5
or 7 (Receive Start Selection), two Periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the
TK (or RK) edge and the signal change. The Max access time is the time between the TK edge and the signal stabili-
zation.
zation.
SSC10 and SSC13.
3. 1.8V domain: V
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 20pF.
4. 3.3V domain: V
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 30pF.
Figure 48-21. Min and Max access time of output signals
SSC
7
TK edge to TF/TD (TK input, TF input)
1.8V domain
3.3V domain
2.8 (+3*t
CPMCK
)
2.1 (+3*t
CPMCK
)
15.4(+3*t
CPMCK
)
11.1 (+3*t
CPMCK
)
ns
Receiver
SSC
8
RF/RD setup time before RK edge (RK input)
1.8V domain
3.3V domain
0
ns
SSC
9
RF/RD hold time after RK edge (RK input)
1.8V domain
3.3V domain
t
CPMCK
ns
SSC
10
RK edge to RF (RK input)
1.8V domain
3.3V domain
2.8
2.1
15.1
10.8
ns
SSC
11
RF/RD setup time before RK edge (RK output)
1.8V domain
3.3V domain
14.5 - t
CPMCK
10.4 - t
CPMCK
ns
SSC
12
RF/RD hold time after RK edge (RK output)
1.8V domain
3.3V domain
t
CPMCK
- 2.7
t
CPMCK
- 1.9
ns
SSC
13
RK edge to RF (RK output)
1.8V domain
3.3V domain
2.1
2.0
13.5
13.2
ns
Table 48-34. SSC Timings
Symbol
Parameter
Conditions
Min
Max
Units
TK (CKI =0)
TF/TD
SSC
0min
TK (CKI =1)
SSC
0max