Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
113
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
14.4.4.2 Wake-up Reset
The wake-up reset occurs when the main supply is down. When the main supply POR output is active, all the reset
signals are asserted except backup_nreset. When the main supply powers up, the POR output is resynchronized on
Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the
ARM processor.
signals are asserted except backup_nreset. When the main supply powers up, the POR output is resynchronized on
Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the
ARM processor.
At the end of this delay, the processor and other reset signals rise. The field RSTTYP in the RSTC_SR is updated to
report a wake-up reset.
report a wake-up reset.
The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the
programmed number of cycles is applicable.
programmed number of cycles is applicable.
When the main supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with
the output of the main supply POR.
the output of the main supply POR.
Figure 14-5. Wake-up Reset
SLCK
periph_nreset
proc_nreset
Main Supply
POR output
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 4 cycles (ERSTL = 1)
MCK
Processor Startup
backup_nreset
Any
Freq.
Resynch.
2 cycles
RSTTYP
XXX
0x1 = WakeUp Reset
XXX