Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The User Reset is entered when a low level is detected on the NRST pin  When a falling edge occurs on NRST (reset
activation), internal reset lines are immediately asserted.

The Processor Reset and the Peripheral Reset are asserted. 

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The
processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, the RSTTYP field of the RSTC_SR is loaded with the value 0x4, indicating
a User Reset.

The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as
programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is
driven low externally, the internal reset lines remain asserted until NRST actually rises. 

SLCK

periph_nreset

proc_nreset

NRST

NRST

(nrst_out)

>= EXTERNAL RESET LENGTH

MCK

Processor Startup 

Any

Freq.

RSTTYP

Any

XXX

Resynch.

2 cycles

0x4 = User Reset