Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
117
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
14.4.5 Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in descending
order:
order:
Backup Reset
Wake-up Reset
User Reset
Watchdog Reset
Software Reset
Particular cases are listed below:
When in User Reset:
A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.
A software reset is impossible, since the processor reset is being activated.
When in Software Reset:
A watchdog event has priority over the current state.
The NRST has no effect.
When in Watchdog Reset:
The processor reset is active and so a Software Reset cannot be programmed.
A User Reset cannot be entered.
14.4.6 Reset Controller Status Register
The Reset Controller Status Register (RSTC_SR) provides several status fields:
RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
SRCMP bit: This bit indicates that a Software Reset Command is in progress and that no further software reset
should be performed until the end of the current one. This bit is automatically cleared at the end of the current
software reset.
should be performed until the end of the current one. This bit is automatically cleared at the end of the current
software reset.
NRSTL bit: This bit gives the level of the NRST pin sampled on each MCK rising edge.
URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit. This transition is also detected on the
Master Clock (MCK) rising edge (see
Master Clock (MCK) rising edge (see
). . Reading the RSTC_SR resets the URSTS bit .
Figure 14-9. Reset Controller Status and Interrupt
MCK
NRST
NRSTL
2 cycle
resynchronization
2 cycle
resynchronization
URSTS
read
RSTC_SR
Peripheral Access
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)