Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

116

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3

 

Slow Clock cycles.

When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:



If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, 
depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a 
User Reset state.



If WDRPROC = 1, only the processor reset is asserted.

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default
and with a period set to a maximum.

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. 

Only if 

WDRPROC = 0

SLCK

periph_nreset

proc_nreset

wd_fault

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup 

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x2 = Watchdog Reset