Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

169

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The slow clock can be generated either by an external 32,768 Hz crystal or by the on-chip 32 kHz RC oscillator. The
32,768 Hz crystal oscillator can be bypassed by setting the bit OSC32BYP to accept an external slow clock on XIN32. 

The internal 32 kHz RC oscillator and the 32,768 Hz oscillator can be enabled by setting to 1, respectively, RCEN bit and
OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source.

RCEN, OSC32EN,OSCSEL and OSC32BYP bits are located in the Slow Clock Control Register (SCKCR) located at
address 0xFFFFFE50 in the backed up part of the System Controller and so are preserved while VDDBU is present.

After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0, BYPASS = 0,
allowing the system to start on the internal 32 kHz RC oscillator.

The programmer controls the slow clock switching by software and so must take precautions during the switching phase.

To switch from internal 32 kHz RC oscillator to the 32,768 Hz crystal, the programmer must execute the following
sequence:



Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power 
Management Controller.



Enable the 32,768 Hz oscillator by setting the bit OSC32EN to 1.



Wait 32,768 Hz Startup Time for clock stabilization (software loop).



Switch from internal 32 kHz RC to 32,768 Hz oscillator by setting the bit OSCSEL to 1.



Wait 5 slow clock cycles for internal resynchronization.



Disable the 32 kHz RC oscillator by setting the bit RCEN to 0.



Switch the master clock back to the slow clock domain

On Chip 
RC OSC

Slow Clock 
SLCK

XIN32

XOUT32

Slow Clock

Oscillator

OSC32EN

RCEN

OSCSEL

OSC32BYP