Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
219
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
23.5.10.2 Interrupt Mode Configuration
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in PIO_AIMER.
23.5.10.3 Edge or Level Detection Configuration
Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in edge detection by default, if they have not been previously configured. Otherwise, lines
0, 1, 2, 6 and 7 must be configured in edge detection by writing 32’h0000_00C7 in PIO_ESR.
0, 1, 2, 6 and 7 must be configured in edge detection by writing 32’h0000_00C7 in PIO_ESR.
23.5.10.4 Falling/Rising Edge or Low/High-Level Detection Configuration
Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writing 32’h0000_00B5 in PIO_REHLSR.
The other lines are configured in falling edge or low-level detection by default if they have not been previously configured.
Otherwise, lines 1, 3 and 6 must be configured in falling edge/low-level detection by writing 32’h0000_004A in
PIO_FELLSR.
Otherwise, lines 1, 3 and 6 must be configured in falling edge/low-level detection by writing 32’h0000_004A in
PIO_FELLSR.
Figure 23-8. Input Change Interrupt Timings When No Additional Interrupt Modes
23.5.11 Programmable I/O Delays
The PIO interface consists of a series of signals driven by peripherals or directly by software. The simultaneous switching
outputs on these busses may lead to a peak of current in the internal and external power supply lines.
outputs on these busses may lead to a peak of current in the internal and external power supply lines.
In order to reduce the current peak in such cases, additional propagation delays can be adjusted independently for pad
buffers by means of configuration registers, PIO_DELAY.
buffers by means of configuration registers, PIO_DELAY.
The additional programmable delays for each supporting range from 0 to 4 ns (Worst Case PVT). The delay can differ
between I/Os supporting this feature. Delay can be modified per programming for each I/O. The minimal additional delay
that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable delay.
between I/Os supporting this feature. Delay can be modified per programming for each I/O. The minimal additional delay
that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable delay.
Only PADs PA[15:11], and PA[20:18] can be configured.
When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of the pad buffers is
the inherent delay of the pad buffer. When programming 0xF in fields, the propagation delay of the corresponding pad is
maximal.
the inherent delay of the pad buffer. When programming 0xF in fields, the propagation delay of the corresponding pad is
maximal.
MCK
Pin Level
Read PIO_ISR
APB Access
PIO_ISR
APB Access