Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
220
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 23-9. Programmable I/O Delays
23.5.12 Programmable I/O Drive
It is possible to configure the I/O drive for pads PA[31:0], PB[18:0], PC[31:0]. For any details, refer to the product
electrical characteristics.
electrical characteristics.
23.5.13 Programmable Schmitt Trigger
It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the Schmitt
trigger is requested when using the QTouch
trigger is requested when using the QTouch
™
Library.
23.5.14 Register Write Protection
To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be write-
protected by setting the WPEN bit in the
protected by setting the WPEN bit in the
(PIO_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the
(PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the PIO_WPSR.
The following registers can be write-protected:
Programmable Delay Line
PIO
PAout[0]
PAin[0]
Programmable Delay Line
Programmable Delay Line
PAout[1]
PAin[1]
PAout[2]
PAin[2]
DELAY2
DELAY1
DELAYx