Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
260
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
24.
Debug Unit (DBGU)
24.1
 Description
The Debug Unit (DBGU) provides a single entry point from the processor for access to all the debug capabilities
of Atmel’s ARM-based systems.
The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal
medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be
used stand-alone for general purpose serial communication. Moreover, the association with  DMA controller channels
permits packet handling for these tasks with processor time reduced to a minimum.
The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the
ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and
generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control.
Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and types
of the on-chip memories, as well as the set of embedded peripherals.
Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access
to the system via the In-circuit Emulator. This permits protection of the code, stored in ROM. 
24.2
Embedded Characteristics
System Peripheral to Facilitate Debug of Atmel
®
 ARM
®
-based Systems 
Composed of Four Functions
Two-pin UART
Debug Communication Channel (DCC) Support
Chip ID Registers
ICE Access Prevention
Two-pin UART
Implemented Features are USART Compatible 
Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Framing and Overrun Error Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Interrupt Generation
Support for Two DMA Channels with Connection to Receiver and Transmitter
Debug Communication Channel Support
Offers Visibility of COMMRX and COMMTX Signals from the ARM Processor
Interrupt Generation
Chip ID Registers
Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals
ICE Access Prevention
Enables Software to Prevent System Access Through the ARM Processor’s ICE
Prevention is made by Asserting the NTRST Line of the ARM Processor’s ICE