Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
262
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
24.4
Product Dependencies
24.4.1 I/O
Lines
Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer
must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.
must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.
24.4.2 Power
Management
Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller.
In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral
identifier used for this purpose is 1.
In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral
identifier used for this purpose is 1.
24.4.3 Interrupt
Source
Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the
Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit.
Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-
time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in
Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit.
Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-
time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in
. This sharing
requires the programmer to determine the source of the interrupt when the source 1 is triggered.
24.5
UART Operations
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with parity).
It has no clock pin.
It has no clock pin.
The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate
generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are
compatible with those of a standard USART.
generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are
compatible with those of a standard USART.
24.5.1 Baud
Rate
Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate
Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART
remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud
rate is Master Clock divided by (16 x 65536).
Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART
remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud
rate is Master Clock divided by (16 x 65536).
Table 24-2. I/O Lines
Instance
Signal
I/O Line
Peripheral
DBGU
DRXD
PA9
A
DBGU
DTXD
PA10
A
Baud Rate
MCK
16
CD
×
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