Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. Every
request attempted by this fixed default master will not cause any arbitration latency whereas other non privileged masters
will still get one latency cycle. This technique is useful for a master that mainly perform single accesses or short bursts
with some Idle cycles in between.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput
whatever is the number of requesting masters.

The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more
masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each
slave differently.

The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types or mixing them for each
slave:

1.

Round-Robin Arbitration (default)

2.

Fixed Priority Arbitration

The resulting algorithm may be complemented by selecting a default master configuration for each slave.

When a re-arbitration must be done, specific conditions apply. See 

.

Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking
and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following
cycles:

1.

Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently 
accessing it.

2.

Single Cycles: When a slave is currently doing a single access.

3.

End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted 
end of burst matches the size of the transfer but is managed differently for undefined length burst. See 

4.

Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access 
is too long and must be broken. See 

In order to optimize AHB burst lengths and arbitration, it may be interesting to set a maximum for undefined length bursts
(INCR). The Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted
end of burst is used as a defined length burst transfer and can be selected from among the following Undefined Length
Burst Type (ULBT) possibilities:

1.

Unlimited: No predicted end of burst is generated and therefore INCR burst transfer will not be broken by this way, 
but will be able to complete unless broken at the Slot Cycle Limit. This is normally the default and should be let as 
is in order to be able to allow full 1 Kilobyte AHB intra-boundary 256-beat word bursts performed by some ATMEL 
AHB masters.

2.

1-beat bursts: Predicted end of burst is generated at each single transfer inside the INCR transfer.

3.

4-beat bursts: Predicted end of burst is generated at the end of each 4-beat boundary inside INCR transfer.

4.

8-beat bursts: Predicted end of burst is generated at the end of each 8-beat boundary inside INCR transfer.

5.

16-beat bursts: Predicted end of burst is generated at the end of each 16-beat boundary inside INCR transfer.

6.

32-beat bursts: Predicted end of burst is generated at the end of each 32-beat boundary inside INCR transfer.

7.

64-beat bursts: Predicted end of burst is generated at the end of each 64-beat boundary inside INCR transfer.

8.

128-beat bursts: Predicted end of burst is generated at the end of each 128-beat boundary inside INCR transfer.