Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Bus Matrix of the AT91SAM9CN12 product manages 6 masters, which means that each master can perform an
access concurrently with others, to an available slave.

Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the
masters have the same decodings.

The Bus Matrix of the AT91SAM9CN12 product manages 5 slaves. Each slave has its own arbiter, allowing a different
arbitration per slave.  

All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing
access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not
wired, and shown as “-” in the following table.

Master 0

ARM926 Instruction

Master 1

ARM926 Data

Master 2&3

DMA Controller

Master 4

USB Host DMA

Master 5

LCD DMA

Slave 0

Internal SRAM

Slave 1

Internal ROM

USB Host User Interface

Slave 2

External Bus Interface

Slave 3

Peripheral Bridge 0

Slave 4

Peripheral Bridge 1

0

Internal SRAM

X

X

X

X

X

1

Internal ROM

USB Host User Interface

X

X

X

-

-

2

External Bus Interface

X

X

X

X

X

3

Peripheral Bridge 0

X

X

X

-

-

4

Peripheral Bridge 1

X

X

X

-

-