Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
312
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
27.5
Application Example
27.5.1 Hardware
Interface
Memory Controller.
Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
2. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3).
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
5. D25-31 and A20, A23-A25, NCS2, NCS4, NCS5 are multiplexed on PD15-PD31.
Table 27-3. EBI Pins and External Static Device Connections
Signals:
EBI_
EBI_
Pins of the Interfaced Device
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit Static
Device
4 x 8-bit
Static
Devices
2 x 16-bit
Static
Devices
32-bit Static
Device
Controller
SMC
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D8 - D15
–
D8 - D15
D8 - D15
D8 - D15
D8 - 15
D8 - 15
D16 - D24
–
–
–
D16 - D23
D16 - D23
D16 - D23
D25 - D31
)
–
–
–
D24 - D31
D24 - D31
D24 - D31
A0/NBS0
A0
–
NLB
–
NLB
BE0
A1/NWR2/NBS2/DQM2
A1
A0
A0
WE
NLB
BE2
A2 - A22
A[2:22]
A[1:21]
A[1:21]
A[0:20]
A[0:20]
A[0:20]
A23 - A25
A[23:25]
A[22:24]
A[22:24]
A[21:23]
A[21:23]
A[21:23]
NCS0
CS
CS
CS
CS
CS
CS
NCS1/DDRSDCS
CS
CS
CS
CS
CS
CS
NCS2
CS
CS
CS
CS
CS
CS
NCS3/NANDCS
CS
CS
CS
CS
CS
CS
NCS4
CS
CS
CS
CS
CS
CS
NCS5
CS
CS
CS
CS
CS
CS
NRD
OE
OE
OE
OE
OE
OE
NWR0/NWE
WE
WE
WE
WE
WE
WE
NWR1/NBS1
–
NUB
NUB
BE1
NWR3/NBS3/DQM3
–
–
–
WE
NUB
BE3