Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

For information on the Static Memory Controller, refer to the Static Memory Controller section.

For information on the DDR2SDR Controller, refer to the DDR2SDRC section.

For information on the PMECC Controller, refer to the PMECC section.

External Bus Interfaces 1 integrate circuitry that interfaces to NAND Flash devices.

The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the
EBI_CSA field in the EBI_CSA Register in the Chip Configuration User Interface to the appropriate value enables the
NAND Flash logic.

 

For details on this register, refer to the Bus Matrix Section. Access to an external NAND Flash device

is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).

The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals
when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the
NCS3 address space. See 

 for more information. For details on these waveforms, refer to the

Static Memory Controller section.