Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
320
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
27.8
Implementation Examples
The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer
web site to check current device availability.
web site to check current device availability.
27.8.1 2x8-bit DDR2 on EBI
27.8.1.1 Hardware Configuration
Figure 27-6.
2x8-bit DDR2 on EBI Configuration
27.8.1.2 Software Configuration
Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Register located in the
bus matrix memory space.
bus matrix memory space.
Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency.
The DDR2 initialization sequence is described in the sub-section “DDR2 Device Initialization” of the DDRSDRC section.
In this case VDDNF can be different from VDDIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16-D31 data
bus. NFD0_ON_D16 is to be set to 1.
bus. NFD0_ON_D16 is to be set to 1.