Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

328

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by
Chip Select, allows boot on 16-bit non-volatile memory at slow clock.

For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on
Flash timings and system bus frequency.

A21
A22

A1
A2
A3
A4
A5
A6
A7
A8

A15

A9

A12
A13

A11

A10

A14

A16

D6

D0

D3
D4

D2

D1

D5

D7

D14

D8

D11
D12

D10

D9

D13

D15

A17

A20

A18
A19

D[0..15]

A[1..22]

NRST
NWE

NCS0
NRD

3V3

3V3

C2

100NF

C2

100NF

C1
100NF

C1
100NF

U1

U1

A0

25

A1

24

A2

23

A3

22

A4

21

A5

20

A6

19

A7

18

A8

8

A9

7

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

48

A17

17

A18

16

A21

9

A20

10

A19

15

WE

11

RESET

12

WP

14

OE

28

CE

26

VPP

13

DQ0

29

DQ1

31

DQ2

33

DQ3

35

DQ4

38

DQ5

40

DQ6

42

DQ7

44

DQ8

30

DQ9

32

DQ10

34

DQ11

36

DQ12

39

DQ13

41

DQ14

43

DQ15

45

VCCQ

47

VSS

27

VSS

46

VCC

37