Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
371
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
30.
Static Memory Controller (SMC)
30.1
Description
The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or
peripheral devices. It has
peripheral devices. It has
6
Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface
with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral
interfacing. Read and write signal waveforms are fully parametrizable.
interfacing. Read and write signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an
automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific
waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up
to 32 bytes.
automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific
waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up
to 32 bytes.
30.2
Embedded Characteristics
6
Chip Selects Available
64-Mbyte Address Space per Chip Select
8-, 16- or 32-bit Data Bus
Word, Halfword, Byte Transfers
Byte Write or Byte Select Lines
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
Compliant with LCD Module
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes